From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60956) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flEiB-0007hR-MB for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:36:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flEi7-0000hz-M4 for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:36:19 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:41236 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1flEi7-0000hf-9s for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:36:15 -0400 From: Stefan Markovic Date: Thu, 2 Aug 2018 16:16:34 +0200 Message-Id: <1533219424-7627-48-git-send-email-stefan.markovic@rt-rk.com> In-Reply-To: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> References: <1533219424-7627-1-git-send-email-stefan.markovic@rt-rk.com> Subject: [Qemu-devel] [PATCH v6 47/77] target/mips: Implement CP0 Config1.WR bit functionality List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: laurent@vivier.eu, riku.voipio@iki.fi, philippe.mathieu.daude@gmail.com, aurelien@aurel32.net, richard.henderson@linaro.org, amarkovic@wavecomp.com, smarkovic@wavecomp.com, pjovanovic@wavecomp.com, pburton@wavecomp.com, arikalo@wavecomp.com From: Stefan Markovic Add testing Config1.WR bit into watch exception handling logic. Signed-off-by: Aleksandar Markovic Signed-off-by: Stefan Markovic --- target/mips/helper.c | 1 + target/mips/translate.c | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/target/mips/helper.c b/target/mips/helper.c index b25e000..f06ffe6 100644 --- a/target/mips/helper.c +++ b/target/mips/helper.c @@ -747,6 +747,7 @@ void mips_cpu_do_interrupt(CPUState *cs) (env->hflags & MIPS_HFLAG_DM)) { cs->exception_index = EXCP_DINT; } + offset = 0x180; switch (cs->exception_index) { case EXCP_DSS: diff --git a/target/mips/translate.c b/target/mips/translate.c index 88d28c8..8306986 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -5609,6 +5609,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -5626,6 +5627,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -6308,6 +6310,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -6325,6 +6328,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -7011,6 +7015,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(dmfc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -7028,6 +7033,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_1e0i(mfc0_watchhi, arg, sel); rn = "WatchHi"; break; @@ -7692,6 +7698,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchlo, arg, sel); rn = "WatchLo"; break; @@ -7709,6 +7716,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 5: case 6: case 7: + CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR)); gen_helper_0e1i(mtc0_watchhi, arg, sel); rn = "WatchHi"; break; -- 1.9.1