From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52122) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1frqlq-0003L3-2N for qemu-devel@nongnu.org; Mon, 20 Aug 2018 16:27:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1frqll-0004BK-G9 for qemu-devel@nongnu.org; Mon, 20 Aug 2018 16:27:25 -0400 Received: from mail-oi0-x231.google.com ([2607:f8b0:4003:c06::231]:33756) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1frqlb-0003PT-JP for qemu-devel@nongnu.org; Mon, 20 Aug 2018 16:27:14 -0400 Received: by mail-oi0-x231.google.com with SMTP id 8-v6so28223526oip.0 for ; Mon, 20 Aug 2018 13:26:58 -0700 (PDT) Sender: Corey Minyard From: minyard@acm.org Date: Mon, 20 Aug 2018 15:26:07 -0500 Message-Id: <1534796770-10295-8-git-send-email-minyard@acm.org> In-Reply-To: <1534796770-10295-1-git-send-email-minyard@acm.org> References: <1534796770-10295-1-git-send-email-minyard@acm.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v2 07/10] Don't delay host status register busy bit when interrupts are enabled List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: "Michael S . Tsirkin" , Corey Minyard , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= From: Corey Minyard Change 880b1ffe6ec2f0ae "smbus: do not immediately complete commands" changed pm_smbus to delay setting the host busy bit until the status register was read, to work around a bug in AMIBIOS. Unfortunately, when interrupts are enabled, the status register will never get read and the processing will never happen. Modify the code to only delay setting the host busy bit if interrupts are not enabled. Signed-off-by: Corey Minyard Cc: Hervé Poussineau Cc: Philippe Mathieu-Daudé --- hw/i2c/pm_smbus.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index 664a6b1..10ba208 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -80,9 +80,6 @@ static void smb_transaction(PMSMBus *s) I2CBus *bus = s->smbus; int ret; - assert(s->smb_stat & STS_HOST_BUSY); - s->smb_stat &= ~STS_HOST_BUSY; - SMBUS_DPRINTF("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot); /* Transaction isn't exec if STS_DEV_ERR bit set */ if ((s->smb_stat & STS_DEV_ERR) != 0) { @@ -209,9 +206,18 @@ error: static void smb_transaction_start(PMSMBus *s) { - /* Do not execute immediately the command ; it will be - * executed when guest will read SMB_STAT register */ - s->smb_stat |= STS_HOST_BUSY; + if (s->smb_ctl & CTL_INTREN) { + smb_transaction(s); + } else { + /* Do not execute immediately the command; it will be + * executed when guest will read SMB_STAT register. This + * is to work around a bug in AMIBIOS (that is working + * around another bug in some specific hardware) where + * it waits for STS_HOST_BUSY to be set before waiting + * checking for status. If STS_HOST_BUSY doesn't get + * set, it gets stuck. */ + s->smb_stat |= STS_HOST_BUSY; + } } static bool @@ -330,6 +336,7 @@ static uint64_t smb_ioport_readb(void *opaque, hwaddr addr, unsigned width) val = s->smb_stat; if (s->smb_stat & STS_HOST_BUSY) { /* execute command now */ + s->smb_stat &= ~STS_HOST_BUSY; smb_transaction(s); } break; -- 2.7.4