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From: "Singh, Brijesh" <brijesh.singh@amd.com>
To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: "Singh, Brijesh" <brijesh.singh@amd.com>,
	Peter Xu <peterx@redhat.com>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Richard Henderson <rth@twiddle.net>,
	Eduardo Habkost <ehabkost@redhat.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	"Lendacky, Thomas" <Thomas.Lendacky@amd.com>,
	"Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>
Subject: [Qemu-devel] [PATCH v5 3/9] x86_iommu/amd: remove V=1 check from amdvi_validate_dte()
Date: Mon, 1 Oct 2018 19:44:32 +0000	[thread overview]
Message-ID: <1538423049-29524-4-git-send-email-brijesh.singh@amd.com> (raw)
In-Reply-To: <1538423049-29524-1-git-send-email-brijesh.singh@amd.com>

Currently, the amdvi_validate_dte() assumes that a valid DTE will
always have V=1. This is not true. The V=1 means that bit[127:1] are
valid. A valid DTE can have IV=1 and V=0 (i.e address translation
disabled and interrupt remapping enabled)

Remove the V=1 check from amdvi_validate_dte(), make the caller
responsible to check for V or IV bits.

This also fixes a bug in existing code that when error is
detected during the translation we'll fail the translation
instead of assuming a passthrough mode.

Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: Tom Lendacky <Thomas.Lendacky@amd.com>
Cc: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
---
 hw/i386/amd_iommu.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c
index 1fd669f..7206bb0 100644
--- a/hw/i386/amd_iommu.c
+++ b/hw/i386/amd_iommu.c
@@ -807,7 +807,7 @@ static inline uint64_t amdvi_get_perms(uint64_t entry)
            AMDVI_DEV_PERM_SHIFT;
 }
 
-/* a valid entry should have V = 1 and reserved bits honoured */
+/* validate that reserved bits are honoured */
 static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid,
                                uint64_t *dte)
 {
@@ -820,7 +820,7 @@ static bool amdvi_validate_dte(AMDVIState *s, uint16_t devid,
         return false;
     }
 
-    return dte[0] & AMDVI_DEV_VALID;
+    return true;
 }
 
 /* get a device table entry given the devid */
@@ -966,8 +966,12 @@ static void amdvi_do_translate(AMDVIAddressSpace *as, hwaddr addr,
         return;
     }
 
-    /* devices with V = 0 are not translated */
     if (!amdvi_get_dte(s, devid, entry)) {
+        return;
+    }
+
+    /* devices with V = 0 are not translated */
+    if (!(entry[0] & AMDVI_DEV_VALID)) {
         goto out;
     }
 
-- 
2.7.4

  parent reply	other threads:[~2018-10-01 19:44 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-01 19:44 [Qemu-devel] [PATCH v5 0/9] x86_iommu/amd: add interrupt remap support Singh, Brijesh
2018-10-01 19:44 ` [Qemu-devel] [PATCH v5 1/9] x86_iommu: move the kernel-irqchip check in common code Singh, Brijesh
2018-10-01 19:44 ` [Qemu-devel] [PATCH v5 2/9] x86_iommu: move vtd_generate_msi_message in common file Singh, Brijesh
2018-10-01 19:44 ` Singh, Brijesh [this message]
2018-10-01 19:44 ` [Qemu-devel] [PATCH v5 4/9] x86_iommu/amd: make the address space naming consistent with intel-iommu Singh, Brijesh
2018-10-01 19:44 ` [Qemu-devel] [PATCH v5 5/9] x86_iommu/amd: Prepare for interrupt remap support Singh, Brijesh
2018-10-08  5:53   ` Peter Xu
2018-10-01 19:44 ` [Qemu-devel] [PATCH v5 6/9] x86_iommu/amd: Add interrupt remap support when VAPIC is not enabled Singh, Brijesh
2018-10-08  5:55   ` Peter Xu
2018-10-01 19:44 ` [Qemu-devel] [PATCH v5 7/9] i386: acpi: add IVHD device entry for IOAPIC Singh, Brijesh
2018-10-01 19:44 ` [Qemu-devel] [PATCH v5 9/9] x86_iommu/amd: Enable Guest virtual APIC support Singh, Brijesh
2018-10-19 14:05 ` [Qemu-devel] [PATCH v5 0/9] x86_iommu/amd: add interrupt remap support Singh, Brijesh
2018-10-19 16:28   ` Michael S. Tsirkin
2018-10-22  9:47     ` Peter Xu

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