From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 10/27] target/mips: Add assembler mnemonics list for MXU ASE
Date: Wed, 17 Oct 2018 14:33:38 +0200 [thread overview]
Message-ID: <1539779635-15445-11-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1539779635-15445-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add a comment that contains a list all MXU instructions,
expressed in assembler mnemonics.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 46655bb..91f63f2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1402,6 +1402,94 @@ enum {
* MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
* the control register.
*
+ * The notation used in MXU assembler mnemonics:
+ *
+ * XRa, XRb, XRc, XRd - MXU registers
+ * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers
+ * s12 - a subfield of an instruction code
+ * strd2 - a subfield of an instruction code
+ * eptn2 - a subfield of an instruction code
+ * eptn3 - a subfield of an instruction code
+ * optn2 - a subfield of an instruction code
+ * optn3 - a subfield of an instruction code
+ * sft4 - a subfield of an instruction code
+ *
+ * Load/Store instructions Multiplication instructions
+ * ----------------------- ---------------------------
+ *
+ * S32LDD XRa, Rb, s12 S32MADD XRa, XRd, Rs, Rt
+ * S32STD XRa, Rb, s12 S32MADDU XRa, XRd, Rs, Rt
+ * S32LDDV XRa, Rb, rc, strd2 S32SUB XRa, XRd, Rs, Rt
+ * S32STDV XRa, Rb, rc, strd2 S32SUBU XRa, XRd, Rs, Rt
+ * S32LDI XRa, Rb, s12 S32MUL XRa, XRd, Rs, Rt
+ * S32SDI XRa, Rb, s12 S32MULU XRa, XRd, Rs, Rt
+ * S32LDIV XRa, Rb, rc, strd2 D16MUL XRa, XRb, XRc, XRd, optn2
+ * S32SDIV XRa, Rb, rc, strd2 D16MULE XRa, XRb, XRc, optn2
+ * S32LDDR XRa, Rb, s12 D16MULF XRa, XRb, XRc, optn2
+ * S32STDR XRa, Rb, s12 D16MAC XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32LDDVR XRa, Rb, rc, strd2 D16MACE XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32STDVR XRa, Rb, rc, strd2 D16MACF XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32LDIR XRa, Rb, s12 D16MADL XRa, XRb, XRc, XRd, aptn2, optn2
+ * S32SDIR XRa, Rb, s12 S16MAD XRa, XRb, XRc, XRd, aptn1, optn2
+ * S32LDIVR XRa, Rb, rc, strd2 Q8MUL XRa, XRb, XRc, XRd
+ * S32SDIVR XRa, Rb, rc, strd2 Q8MULSU XRa, XRb, XRc, XRd
+ * S16LDD XRa, Rb, s10, eptn2 Q8MAC XRa, XRb, XRc, XRd, aptn2
+ * S16STD XRa, Rb, s10, eptn2 Q8MACSU XRa, XRb, XRc, XRd, aptn2
+ * S16LDI XRa, Rb, s10, eptn2 Q8MADL XRa, XRb, XRc, XRd, aptn2
+ * S16SDI XRa, Rb, s10, eptn2
+ * S8LDD XRa, Rb, s8, eptn3
+ * S8STD XRa, Rb, s8, eptn3 Addition and subtraction instructions
+ * S8LDI XRa, Rb, s8, eptn3 -------------------------------------
+ * S8SDI XRa, Rb, s8, eptn3
+ * LXW Rd, Rs, Rt, strd2 D32ADD XRa, XRb, XRc, XRd, eptn2
+ * LXH Rd, Rs, Rt, strd2 D32ADDC XRa, XRb, XRc, XRd
+ * LXHU Rd, Rs, Rt, strd2 D32ACC XRa, XRb, XRc, XRd, eptn2
+ * LXB Rd, Rs, Rt, strd2 D32ACCM XRa, XRb, XRc, XRd, eptn2
+ * LXBU Rd, Rs, Rt, strd2 D32ASUM XRa, XRb, XRc, XRd, eptn2
+ * S32CPS XRa, XRb, XRc
+ * Q16ADD XRa, XRb, XRc, XRd, eptn2, optn2
+ * Comparison instructions Q16ACC XRa, XRb, XRc, XRd, eptn2
+ * ----------------------- Q16ACCM XRa, XRb, XRc, XRd, eptn2
+ * D16ASUM XRa, XRb, XRc, XRd, eptn2
+ * S32MAX XRa, XRb, XRc D16CPS XRa, XRb,
+ * S32MIN XRa, XRb, XRc D16AVG XRa, XRb, XRc
+ * S32SLT XRa, XRb, XRc D16AVGR XRa, XRb, XRc
+ * S32MOVZ XRa, XRb, XRc Q8ADD XRa, XRb, XRc, eptn2
+ * S32MOVN XRa, XRb, XRc Q8ADDE XRa, XRb, XRc, XRd, eptn2
+ * D16MAX XRa, XRb, XRc Q8ACCE XRa, XRb, XRc, XRd, eptn2
+ * D16MIN XRa, XRb, XRc Q8ABD XRa, XRb, XRc
+ * D16SLT XRa, XRb, XRc Q8SAD XRa, XRb, XRc, XRd
+ * D16MOVZ XRa, XRb, XRc Q8AVG XRa, XRb, XRc
+ * D16MOVN XRa, XRb, XRc Q8AVGR XRa, XRb, XRc
+ * Q8MAX XRa, XRb, XRc D8SUM XRa, XRb, XRc, XRd
+ * Q8MIN XRa, XRb, XRc D8SUMC XRa, XRb, XRc, XRd
+ * Q8SLT XRa, XRb, XRc
+ * Q8SLTU XRa, XRb, XRc
+ * Q8MOVZ XRa, XRb, XRc Shift instructions
+ * Q8MOVN XRa, XRb, XRc ------------------
+ *
+ * D32SLL XRa, XRb, XRc, XRd, sft4
+ * Bitwise instructions D32SLR XRa, XRb, XRc, XRd, sft4
+ * -------------------- D32SAR XRa, XRb, XRc, XRd, sft4
+ * D32SARL XRa, XRb, XRc, sft4
+ * S32NOR XRa, XRb, XRc D32SLLV XRa, XRb, Rb
+ * S32AND XRa, XRb, XRc D32SLRV XRa, XRb, Rb
+ * S32XOR XRa, XRb, XRc D32SARV XRa, XRb, Rb
+ * S32OR XRa, XRb, XRc D32SARW XRa, XRb, XRc, Rb
+ * Q16SLL XRa, XRb, XRc, XRd, sft4
+ * Q16SLR XRa, XRb, XRc, XRd, sft4
+ * Miscelaneous instructions Q16SAR XRa, XRb, XRc, XRd, sft4
+ * ------------------------- Q16SLLV XRa, XRb, Rb
+ * Q16SLRV XRa, XRb, Rb
+ * S32SFL XRa, XRb, XRc, XRd, optn2 Q16SARV XRa, XRb, Rb
+ * S32ALN XRa, XRb, XRc, Rb
+ * S32ALNI XRa, XRb, XRc, s3
+ * S32LUI XRa, s8, optn3 Move instructions
+ * S32EXTR XRa, XRb, Rb, bits5 -----------------
+ * S32EXTRV XRa, XRb, Rs, Rt
+ * Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb
+ * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
+ *
* Compiled after:
*
* "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
--
2.7.4
next prev parent reply other threads:[~2018-10-17 12:35 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-17 12:33 [Qemu-devel] [PULL 00/27]MIPS pull request for October 2018 - part 1 Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 01/27] mailmap: Add an item for Yongbok Kim Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 02/27] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 03/27] elf: Add MIPS_ABI_FP_XXX constants Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 04/27] elf: Add Mips_elf_abiflags_v0 structure Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 05/27] linux-user: Add MIPS-specific prctl() options Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl() Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 07/27] target/mips: Add a comment with an overview of CP0 registers Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 08/27] target/mips: Add a comment before each CP0 register section in cpu.h Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE Aleksandar Markovic
2018-10-17 12:33 ` Aleksandar Markovic [this message]
2018-10-17 12:33 ` [Qemu-devel] [PULL 11/27] target/mips: Add organizational chart " Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 12/27] target/mips: Add opcode values " Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' flag holder size Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 14/27] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags) Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 ASE Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 16/27] target/mips: Add availability control " Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 17/27] target/mips: Improve DSP R2/R3-related naming Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 18/27] target/mips: Add CP0 Config2 to DisasContext Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 19/27] target/mips: Add CP0 PWBase register Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 20/27] target/mips: Add CP0 PWField register Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 21/27] target/mips: Add CP0 PWSize register Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 22/27] target/mips: Add CP0 PWCtl register Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 23/27] target/mips: Add reset state for PWSize and PWField registers Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 24/27] target/mips: Implement hardware page table walker for MIPS32 Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
2018-10-18 15:33 ` [Qemu-devel] [PULL 00/27]MIPS pull request for October 2018 - part 1 Peter Maydell
2018-10-18 15:50 ` [Qemu-devel] ?==?utf-8?q? [PULL?==?utf-8?q? " Aleksandar Markovic
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