From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 11/27] target/mips: Add organizational chart of MXU ASE
Date: Wed, 17 Oct 2018 14:33:39 +0200 [thread overview]
Message-ID: <1539779635-15445-12-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1539779635-15445-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add a comment that contains an organizational chart of MXU ASE
instructions.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 156 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 156 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 91f63f2..45ed1d9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1490,6 +1490,162 @@ enum {
* Q16SCOP XRa, XRb, XRc, XRd S32M2I XRa, Rb
* Q16SAT XRa, XRb, XRc S32I2M XRa, Rb
*
+ *
+ * bits
+ * 05..00
+ *
+ * ┌─ 000000 ─ OPC_MXU_S32MADD
+ * ├─ 000001 ─ OPC_MXU_S32MADDU
+ * ├─ 000010 ─ <not assigned>
+ * │ 20..18 (25..21 must be 0)
+ * ├─ 000011 ─ OPC_MXU__POOL00 ─┬─ 000 ─ OPC_MXU_S32MAX
+ * │ ├─ 001 ─ OPC_MXU_S32MIN
+ * │ ├─ 010 ─ OPC_MXU_D16MAX
+ * │ ├─ 011 ─ OPC_MXU_D16MIN
+ * │ ├─ 100 ─ OPC_MXU_Q8MAX
+ * │ ├─ 101 ─ OPC_MXU_Q8MIN
+ * │ ├─ 110 ─ OPC_MXU_Q8SLT
+ * │ └─ 111 ─ OPC_MXU_Q8SLTU
+ * ├─ 000100 ─ OPC_MXU_S32MSUB
+ * ├─ 000101 ─ OPC_MXU_S32MSUBU 20..18 (25..21 must be 0,
+ * │ except for Q8ADD)
+ * ├─ 000110 ─ OPC_MXU__POOL01 ─┬─ 000 ─ OPC_MXU_S32SLT
+ * │ ├─ 001 ─ OPC_MXU_D16SLT
+ * │ ├─ 010 ─ OPC_MXU_D16AVG
+ * │ ├─ 011 ─ OPC_MXU_D16AVGR
+ * │ ├─ 100 ─ OPC_MXU_Q8AVG
+ * │ ├─ 101 ─ OPC_MXU_Q8AVGR
+ * │ └─ 111 ─ OPC_MXU_Q8ADD
+ * │
+ * │ 20..18 (25..21 must be 0)
+ * ├─ 000111 ─ OPC_MXU__POOL02 ─┬─ 000 ─ OPC_MXU_S32CPS
+ * │ ├─ 010 ─ OPC_MXU_D16CPS
+ * │ ├─ 100 ─ OPC_MXU_Q8ABD
+ * │ └─ 110 ─ OPC_MXU_Q16SAT
+ * ├─ 001000 ─ OPC_MXU_D16MUL
+ * │ 25..24
+ * ├─ 001001 ─ OPC_MXU__POOL03 ─┬─ 00 ─ OPC_MXU_D16MULF
+ * │ └─ 01 ─ OPC_MXU_D16MULE
+ * ├─ 001010 ─ OPC_MXU_D16MAC
+ * ├─ 001011 ─ OPC_MXU_D16MACF
+ * ├─ 001100 ─ OPC_MXU_D16MADL
+ * │ 25..24
+ * ├─ 001101 ─ OPC_MXU__POOL04 ─┬─ 00 ─ OPC_MXU_S16MAD
+ * │ └─ 01 ─ OPC_MXU_S16MAD_1
+ * ├─ 001110 ─ OPC_MXU_Q16ADD
+ * ├─ 001111 ─ OPC_MXU_D16MACE
+ * │ 23
+ * ├─ 010000 ─ OPC_MXU__POOL05 ─┬─ 0 ─ OPC_MXU_S32LDD
+ * │ └─ 1 ─ OPC_MXU_S32LDDR
+ * │
+ * │ 23
+ * ├─ 010001 ─ OPC_MXU__POOL06 ─┬─ 0 ─ OPC_MXU_S32STD
+ * │ └─ 1 ─ OPC_MXU_S32STDR
+ * │
+ * │ 13..10
+ * ├─ 010010 ─ OPC_MXU__POOL07 ─┬─ 0000 ─ OPC_MXU_S32LDDV
+ * │ └─ 0001 ─ OPC_MXU_S32LDDVR
+ * │
+ * │ 13..10
+ * ├─ 010011 ─ OPC_MXU__POOL08 ─┬─ 0000 ─ OPC_MXU_S32TDV
+ * │ └─ 0001 ─ OPC_MXU_S32TDVR
+ * │
+ * │ 23
+ * ├─ 010100 ─ OPC_MXU__POOL09 ─┬─ 0 ─ OPC_MXU_S32LDI
+ * │ └─ 1 ─ OPC_MXU_S32LDIR
+ * │
+ * │ 23
+ * ├─ 010101 ─ OPC_MXU__POOL10 ─┬─ 0 ─ OPC_MXU_S32SDI
+ * │ └─ 1 ─ OPC_MXU_S32SDIR
+ * │
+ * │ 13..10
+ * ├─ 010110 ─ OPC_MXU__POOL11 ─┬─ 0000 ─ OPC_MXU_S32LDIV
+ * │ └─ 0001 ─ OPC_MXU_S32LDIVR
+ * │
+ * │ 13..10
+ * ├─ 010111 ─ OPC_MXU__POOL12 ─┬─ 0000 ─ OPC_MXU_S32SDIV
+ * │ └─ 0001 ─ OPC_MXU_S32SDIVR
+ * ├─ 011000 ─ OPC_MXU_D32ADD
+ * │
+ * MXU ├─ 011001 ─ OPC_MXU__POOL13 ─┬─ 00 ─ OPC_MXU_D32ACC
+ * opcodes ─┤ ├─ 01 ─ OPC_MXU_D32ACCM
+ * │ └─ 10 ─ OPC_MXU_D32ASUM
+ * ├─ 011010 ─ <not assigned>
+ * │
+ * ├─ 011011 ─ OPC_MXU__POOL14 ─┬─ 00 ─ OPC_MXU_Q16ACC
+ * │ ├─ 01 ─ OPC_MXU_Q16ACCM
+ * │ └─ 10 ─ OPC_MXU_Q16ASUM
+ * │
+ * │
+ * ├─ 011100 ─ OPC_MXU__POOL15 ─┬─ 00 ─ OPC_MXU_Q8ADDE
+ * │ ├─ 01 ─ OPC_MXU_D8SUM
+ * ├─ 011101 ─ OPC_MXU_Q8ACCE └─ 10 ─ OPC_MXU_D8SUMC
+ * ├─ 011110 ─ <not assigned>
+ * ├─ 011111 ─ <not assigned>
+ * ├─ 100000 ─ <not assigned>
+ * ├─ 100001 ─ <not assigned>
+ * ├─ 100010 ─ OPC_MXU_S8LDD
+ * ├─ 100011 ─ OPC_MXU_S8STD
+ * ├─ 100100 ─ OPC_MXU_S8LDI
+ * ├─ 100101 ─ OPC_MXU_S8SDI
+ * │
+ * ├─ 100110 ─ OPC_MXU__POOL16 ─┬─ 00 ─ OPC_MXU_S32MUL
+ * │ ├─ 00 ─ OPC_MXU_S32MULU
+ * │ ├─ 00 ─ OPC_MXU_S32EXTR
+ * │ └─ 00 ─ OPC_MXU_S32EXTRV
+ * │
+ * │
+ * ├─ 100111 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_D32SARW
+ * │ ├─ 001 ─ OPC_MXU_S32ALN
+ * ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI
+ * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_S32NOR
+ * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_S32AND
+ * ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR
+ * ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR
+ * ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI
+ * ├─ 101000 ─ <not assigned>
+ * ├─ 101001 ─ <not assigned>
+ * ├─ 101010 ─ <not assigned>
+ * ├─ 101011 ─ <not assigned>
+ * ├─ 101100 ─ <not assigned>
+ * ├─ 101101 ─ <not assigned>
+ * ├─ 101110 ─ OPC_MXU_S32M2I
+ * ├─ 101111 ─ OPC_MXU_S32I2M
+ * ├─ 110000 ─ OPC_MXU_D32SLL
+ * ├─ 110001 ─ OPC_MXU_D32SLR
+ * ├─ 110010 ─ OPC_MXU_D32SARL
+ * ├─ 110011 ─ OPC_MXU_D32SAR
+ * ├─ 110100 ─ OPC_MXU_Q16SLL
+ * ├─ 110101 ─ OPC_MXU_Q16SLR
+ * ├─ 110110 ─ OPC_MXU__POOL18 ─┬─ 000 ─ OPC_MXU_D32SLLV
+ * │ ├─ 001 ─ OPC_MXU_D32SLRV
+ * │ ├─ 010 ─ OPC_MXU_D32SARV
+ * │ ├─ 011 ─ OPC_MXU_Q16SLLV
+ * │ ├─ 100 ─ OPC_MXU_Q16SLRV
+ * │ └─ 101 ─ OPC_MXU_Q16SARV
+ * ├─ 110111 ─ OPC_MXU_Q16SAR
+ * │
+ * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL
+ * │ └─ 01 ─ OPC_MXU_Q8MULSU
+ * │
+ * │
+ * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ
+ * │ ├─ 001 ─ OPC_MXU_Q8MOVN
+ * │ ├─ 010 ─ OPC_MXU_D16MOVZ
+ * │ ├─ 011 ─ OPC_MXU_D16MOVN
+ * │ ├─ 100 ─ OPC_MXU_S32MOVZ
+ * │ └─ 101 ─ OPC_MXU_S32MOV
+ * │
+ * │
+ * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC
+ * │ └─ 10 ─ OPC_MXU_Q8MACSU
+ * ├─ 111011 ─ OPC_MXU_Q16SCOP
+ * ├─ 111100 ─ OPC_MXU_Q8MADL
+ * ├─ 111101 ─ OPC_MXU_S32SFL
+ * ├─ 111110 ─ OPC_MXU_Q8SAD
+ * └─ 111111 ─ <not assigned>
+ *
+ *
* Compiled after:
*
* "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
--
2.7.4
next prev parent reply other threads:[~2018-10-17 12:35 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-17 12:33 [Qemu-devel] [PULL 00/27]MIPS pull request for October 2018 - part 1 Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 01/27] mailmap: Add an item for Yongbok Kim Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 02/27] elf: Fix PT_MIPS_XXX constants Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 03/27] elf: Add MIPS_ABI_FP_XXX constants Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 04/27] elf: Add Mips_elf_abiflags_v0 structure Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 05/27] linux-user: Add MIPS-specific prctl() options Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl() Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 07/27] target/mips: Add a comment with an overview of CP0 registers Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 08/27] target/mips: Add a comment before each CP0 register section in cpu.h Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 10/27] target/mips: Add assembler mnemonics list for " Aleksandar Markovic
2018-10-17 12:33 ` Aleksandar Markovic [this message]
2018-10-17 12:33 ` [Qemu-devel] [PULL 12/27] target/mips: Add opcode values of " Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' flag holder size Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 14/27] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags) Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 15/27] target/mips: Add bit definitions for DSP R3 ASE Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 16/27] target/mips: Add availability control " Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 17/27] target/mips: Improve DSP R2/R3-related naming Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 18/27] target/mips: Add CP0 Config2 to DisasContext Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 19/27] target/mips: Add CP0 PWBase register Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 20/27] target/mips: Add CP0 PWField register Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 21/27] target/mips: Add CP0 PWSize register Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 22/27] target/mips: Add CP0 PWCtl register Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 23/27] target/mips: Add reset state for PWSize and PWField registers Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 24/27] target/mips: Implement hardware page table walker for MIPS32 Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S> Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 26/27] target/mips: Fix misplaced 'break' in handling of NM_SHRA_R_PH Aleksandar Markovic
2018-10-17 12:33 ` [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions Aleksandar Markovic
2018-10-18 15:33 ` [Qemu-devel] [PULL 00/27]MIPS pull request for October 2018 - part 1 Peter Maydell
2018-10-18 15:50 ` [Qemu-devel] ?==?utf-8?q? [PULL?==?utf-8?q? " Aleksandar Markovic
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