From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53770) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gL5KR-0004X3-8c for qemu-devel@nongnu.org; Fri, 09 Nov 2018 06:52:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gL5KQ-00077Y-9G for qemu-devel@nongnu.org; Fri, 09 Nov 2018 06:51:59 -0500 Received: from mga05.intel.com ([192.55.52.43]:56447) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gL5KP-00074h-V0 for qemu-devel@nongnu.org; Fri, 09 Nov 2018 06:51:58 -0500 From: Yu Zhang Date: Fri, 9 Nov 2018 19:49:47 +0800 Message-Id: <1541764187-10732-4-git-send-email-yu.c.zhang@linux.intel.com> In-Reply-To: <1541764187-10732-1-git-send-email-yu.c.zhang@linux.intel.com> References: <1541764187-10732-1-git-send-email-yu.c.zhang@linux.intel.com> Subject: [Qemu-devel] [PATCH v1 3/3] intel-iommu: search iotlb for levels supported by the address width. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Peter Xu This patch updates vtd_lookup_iotlb() to search cached mappings only for all page levels supported by address width of current vIOMMU. Also, to cover 57-bit width, the shift of source id(VTD_IOTLB_SID_SHIFT) and of page level(VTD_IOTLB_LVL_SHIFT) are enlarged by 9 - the stride of one paging structure level. Signed-off-by: Yu Zhang --- Cc: "Michael S. Tsirkin" Cc: Marcel Apfelbaum Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: Peter Xu --- hw/i386/intel_iommu.c | 5 +++-- hw/i386/intel_iommu_internal.h | 7 ++----- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 9cdf755..ce7e17e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -254,11 +254,12 @@ static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level) static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id, hwaddr addr) { - VTDIOTLBEntry *entry; + VTDIOTLBEntry *entry = NULL; uint64_t key; int level; + int max_level = (s->aw_bits - VTD_PAGE_SHIFT_4K) / VTD_SL_LEVEL_BITS; - for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) { + for (level = VTD_SL_PT_LEVEL; level < max_level; level++) { key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level), source_id, level); entry = g_hash_table_lookup(s->iotlb, &key); diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index a7ef24b..bdf2b7c 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -114,8 +114,8 @@ VTD_INTERRUPT_ADDR_FIRST + 1) /* The shift of source_id in the key of IOTLB hash table */ -#define VTD_IOTLB_SID_SHIFT 36 -#define VTD_IOTLB_LVL_SHIFT 52 +#define VTD_IOTLB_SID_SHIFT 45 +#define VTD_IOTLB_LVL_SHIFT 61 #define VTD_IOTLB_MAX_SIZE 1024 /* Max size of the hash table */ /* IOTLB_REG */ @@ -450,9 +450,6 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SL_LEVEL_BITS 9 /* Second Level Paging Structure */ -#define VTD_SL_PML4_LEVEL 4 -#define VTD_SL_PDP_LEVEL 3 -#define VTD_SL_PD_LEVEL 2 #define VTD_SL_PT_LEVEL 1 #define VTD_SL_PT_ENTRY_NR 512 -- 1.9.1