From: Yu Zhang <yu.c.zhang@linux.intel.com>
To: qemu-devel@nongnu.org
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
Igor Mammedov <imammedo@redhat.com>,
Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Richard Henderson <rth@twiddle.net>,
Eduardo Habkost <ehabkost@redhat.com>,
Peter Xu <peterx@redhat.com>
Subject: [Qemu-devel] [PATCH v2 0/3] intel-iommu: add support for 5-level virtual IOMMU.
Date: Wed, 14 Nov 2018 14:04:41 +0800 [thread overview]
Message-ID: <1542175484-2742-1-git-send-email-yu.c.zhang@linux.intel.com> (raw)
Intel's upcoming processors will extend maximum linear address width to
57 bits, and introduce 5-level paging for CPU. Meanwhile, the platform
will also extend the maximum guest address width for IOMMU to 57 bits,
thus introducing the 5-level paging for 2nd level translation(See chapter
3 in Intel Virtualization Technology for Directed I/O).
This patch series extends the current logic to support a wider address width.
A 5-level paging capable IOMMU(for 2nd level translation) can be rendered
with configuration "device intel-iommu,x-aw-bits=57".
Also, kvm-unit-tests were updated to verify this patch series. Patch for
the test was sent out at: https://www.spinics.net/lists/kvm/msg177425.html.
Note: this patch series checks the existance of 5-level paging in the host
and in the guest, and rejects configurations for 57-bit IOVA if either check
fails(VTD-d hardware shall not support 57-bit IOVA on platforms without CPU
5-level paging). However, current vIOMMU implementation still lacks logic to
check against the physical IOMMU capability, future enhancements are expected
to do this.
Changes in V2:
- Address comments from Peter Xu: add haw member in vtd_page_walk_info.
- Address comments from Peter Xu: only searches for 4K/2M/1G mappings in
iotlb are meaningful.
- Address comments from Peter Xu: cover letter changes(e.g. mention the test
patch in kvm-unit-tests).
- Coding style changes.
Yu Zhang (3):
intel-iommu: differentiate host address width from IOVA address width.
intel-iommu: extend VTD emulation to allow 57-bit IOVA address width.
intel-iommu: extend iotlb search logic to cover 57-bit IOVA.
---
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Peter Xu <peterx@redhat.com>
hw/i386/acpi-build.c | 2 +-
hw/i386/intel_iommu.c | 96 +++++++++++++++++++++++++++++-------------
hw/i386/intel_iommu_internal.h | 10 ++++-
include/hw/i386/intel_iommu.h | 10 +++--
4 files changed, 81 insertions(+), 37 deletions(-)
--
1.9.1
next reply other threads:[~2018-11-14 6:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-14 6:04 Yu Zhang [this message]
2018-11-14 6:04 ` [Qemu-devel] [PATCH v2 1/3] intel-iommu: differentiate host address width from IOVA address width Yu Zhang
2018-11-14 6:33 ` Peter Xu
2018-11-14 6:04 ` [Qemu-devel] [PATCH v2 2/3] intel-iommu: extend VTD emulation to allow 57-bit " Yu Zhang
2018-11-14 6:36 ` Peter Xu
2018-11-14 6:04 ` [Qemu-devel] [PATCH v2 3/3] intel-iommu: extend iotlb search logic to cover 57-bit IOVA Yu Zhang
2018-11-14 6:41 ` Peter Xu
2018-11-14 6:48 ` Yu Zhang
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