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From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com, laurent@vivier.eu
Subject: [Qemu-devel] [PULL v2 09/11] target/mips: Rename MMI-related functions
Date: Sat, 17 Nov 2018 19:38:26 +0100	[thread overview]
Message-ID: <1542479908-20067-10-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1542479908-20067-1-git-send-email-aleksandar.markovic@rt-rk.com>

From: Aleksandar Markovic <amarkovic@wavecomp.com>

Rename MMI-related functions.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 98dc468..e9c23a5 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -26464,7 +26464,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t opc = MASK_MMI0(ctx->opcode);
 
@@ -26503,7 +26503,7 @@ static void decode_tx79_mmi0(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi1(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t opc = MASK_MMI1(ctx->opcode);
 
@@ -26535,7 +26535,7 @@ static void decode_tx79_mmi1(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi2(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t opc = MASK_MMI2(ctx->opcode);
 
@@ -26571,7 +26571,7 @@ static void decode_tx79_mmi2(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t opc = MASK_MMI3(ctx->opcode);
 
@@ -26598,7 +26598,7 @@ static void decode_tx79_mmi3(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t opc = MASK_MMI(ctx->opcode);
     int rs = extract32(ctx->opcode, 21, 5);
@@ -26607,16 +26607,16 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
 
     switch (opc) {
     case MMI_OPC_CLASS_MMI0:
-        decode_tx79_mmi0(env, ctx);
+        decode_mmi0(env, ctx);
         break;
     case MMI_OPC_CLASS_MMI1:
-        decode_tx79_mmi1(env, ctx);
+        decode_mmi1(env, ctx);
         break;
     case MMI_OPC_CLASS_MMI2:
-        decode_tx79_mmi2(env, ctx);
+        decode_mmi2(env, ctx);
         break;
     case MMI_OPC_CLASS_MMI3:
-        decode_tx79_mmi3(env, ctx);
+        decode_mmi3(env, ctx);
         break;
     case MMI_OPC_MULT1:
     case MMI_OPC_MULTU1:
@@ -26656,12 +26656,12 @@ static void decode_tx79_mmi(CPUMIPSState *env, DisasContext *ctx)
     }
 }
 
-static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
+static void gen_mmi_lq(CPUMIPSState *env, DisasContext *ctx)
 {
     generate_exception_end(ctx, EXCP_RI);    /* TODO: MMI_OPC_LQ */
 }
 
-static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
+static void gen_mmi_sq(DisasContext *ctx, int base, int rt, int offset)
 {
     generate_exception_end(ctx, EXCP_RI);    /* TODO: MMI_OPC_SQ */
 }
@@ -26687,7 +26687,7 @@ static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
  * In user mode, QEMU must verify the upper and lower 11 bits to distinguish
  * between SQ and RDHWR, as the Linux kernel does.
  */
-static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx)
+static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
 {
     int base = extract32(ctx->opcode, 21, 5);
     int rt = extract32(ctx->opcode, 16, 5);
@@ -26705,7 +26705,7 @@ static void decode_tx79_sq(CPUMIPSState *env, DisasContext *ctx)
     }
 #endif
 
-    gen_tx79_sq(ctx, base, rt, offset);
+    gen_mmi_sq(ctx, base, rt, offset);
 }
 
 static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
@@ -28014,7 +28014,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case OPC_SPECIAL2:
         if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
-            decode_tx79_mmi(env, ctx);
+            decode_mmi(env, ctx);
         } else if (ctx->insn_flags & ASE_MXU) {
             decode_opc_mxu(env, ctx);
         } else {
@@ -28023,7 +28023,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case OPC_SPECIAL3:
         if (ctx->insn_flags & INSN_R5900) {
-            decode_tx79_sq(env, ctx);    /* MMI_OPC_SQ */
+            decode_mmi_sq(env, ctx);    /* MMI_OPC_SQ */
         } else {
             decode_opc_special3(env, ctx);
         }
@@ -28698,7 +28698,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
         break;
     case OPC_MSA: /* OPC_MDMX */
         if (ctx->insn_flags & INSN_R5900) {
-            decode_tx79_lq(env, ctx);    /* MMI_OPC_LQ */
+            gen_mmi_lq(env, ctx);    /* MMI_OPC_LQ */
         } else {
             /* MDMX: Not implemented. */
             gen_msa(env, ctx);
-- 
2.7.4

  parent reply	other threads:[~2018-11-17 18:38 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-17 18:38 [Qemu-devel] [PULL v2 00/11] MIPS queue for November 2018 (for QEMU 3.1-rc2) - v2 Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 01/11] linux-user: Update MIPS specific prctl() implementation Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 02/11] target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1 Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 03/11] target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1 Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 04/11] target/mips: Fix decoding mechanism of special R5900 opcodes Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 05/11] target/mips: Guard check_insn_opc_user_only with INSN_R5900 check Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 06/11] target/mips: Guard check_insn " Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 07/11] target/mips: Rename MMI-related masks Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 08/11] target/mips: Rename MMI-related opcodes Aleksandar Markovic
2018-11-17 18:38 ` Aleksandar Markovic [this message]
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 10/11] target/mips: Disable R5900 support Aleksandar Markovic
2018-11-17 18:38 ` [Qemu-devel] [PULL v2 11/11] MAINTAINERS: Add Stefan Markovic as a MIPS reviewer Aleksandar Markovic
2018-11-19 11:18 ` [Qemu-devel] [PULL v2 00/11] MIPS queue for November 2018 (for QEMU 3.1-rc2) - v2 Peter Maydell

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