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From: Alex Williamson <alex.williamson@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Michael S. Tsirkin" <mst@redhat.com>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,
	Eric Auger <eric.auger@redhat.com>
Subject: [Qemu-devel] [PATCH v5 8/8] pcie: Fast PCIe root ports for new machines
Date: Wed, 12 Dec 2018 12:40:09 -0700	[thread overview]
Message-ID: <154464360920.9828.6723013766146630942.stgit@gimli.home> (raw)
In-Reply-To: <154464279386.9828.10219496338109023342.stgit@gimli.home>

Change the default speed and width for new machine types to the
fastest and widest currently supported.  This should be compatible to
the PCIe 4.0 spec.  Pre-QEMU-4.0 machine types remain at 2.5GT/s, x1
width.

Cc: Michael S. Tsirkin <mst@redhat.com>
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
---
 hw/pci-bridge/gen_pcie_root_port.c |    4 ++--
 include/hw/compat.h                |   10 +++++++++-
 2 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c
index ca5418a89dd2..9766edb44596 100644
--- a/hw/pci-bridge/gen_pcie_root_port.c
+++ b/hw/pci-bridge/gen_pcie_root_port.c
@@ -125,9 +125,9 @@ static Property gen_rp_props[] = {
     DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
                      res_reserve.mem_pref_64, -1),
     DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
-                                speed, PCIE_LINK_SPEED_2_5),
+                                speed, PCIE_LINK_SPEED_16),
     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
-                                width, PCIE_LINK_WIDTH_1),
+                                width, PCIE_LINK_WIDTH_32),
     DEFINE_PROP_END_OF_LIST()
 };
 
diff --git a/include/hw/compat.h b/include/hw/compat.h
index 70958328fe7a..3ca85b037c04 100644
--- a/include/hw/compat.h
+++ b/include/hw/compat.h
@@ -2,7 +2,15 @@
 #define HW_COMPAT_H
 
 #define HW_COMPAT_3_1 \
-    /* empty */
+    {\
+        .driver   = "pcie-root-port",\
+        .property = "x-speed",\
+        .value    = "2_5",\
+    },{\
+        .driver   = "pcie-root-port",\
+        .property = "x-width",\
+        .value    = "1",\
+    },
 
 #define HW_COMPAT_3_0 \
     /* empty */

      parent reply	other threads:[~2018-12-12 19:40 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-12 19:38 [Qemu-devel] [PATCH v5 0/8] pcie: Enhanced link speed and width support Alex Williamson
2018-12-12 19:38 ` [Qemu-devel] [PATCH v5 1/8] pcie: Create enums for link speed and width Alex Williamson
2018-12-12 19:38 ` [Qemu-devel] [PATCH v5 2/8] pci: Sync PCIe downstream port LNKSTA on read Alex Williamson
2018-12-12 19:39 ` [Qemu-devel] [PATCH v5 3/8] qapi: Define PCIe link speed and width properties Alex Williamson
2018-12-12 19:39 ` [Qemu-devel] [PATCH v5 4/8] pcie: Add link speed and width fields to PCIESlot Alex Williamson
2018-12-12 19:39 ` [Qemu-devel] [PATCH v5 5/8] pcie: Fill PCIESlot link fields to support higher speeds and widths Alex Williamson
2018-12-12 19:39 ` [Qemu-devel] [PATCH v5 6/8] pcie: Allow generic PCIe root port to specify link speed and width Alex Williamson
2018-12-18  1:29   ` Michael S. Tsirkin
2018-12-18  1:44     ` Alex Williamson
2018-12-18  1:47       ` Michael S. Tsirkin
2018-12-18  1:54         ` Alex Williamson
2018-12-18  2:27           ` Michael S. Tsirkin
2018-12-12 19:39 ` [Qemu-devel] [PATCH v5 7/8] vfio/pci: Remove PCIe Link Status emulation Alex Williamson
2018-12-12 19:40 ` Alex Williamson [this message]

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