From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PULL v2 02/12] target/mips: Add preprocessor constants for 32 major CP0 registers
Date: Fri, 18 Jan 2019 17:59:35 +0100 [thread overview]
Message-ID: <1547830785-7079-3-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Add preprocessor constants for 32 major CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 6c2a7e4..b095422 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -233,6 +233,38 @@ typedef struct mips_def_t mips_def_t;
* 7 TagLo TagHi KScratch<n>
*
*/
+#define CPO_REGISTER_00 0
+#define CPO_REGISTER_01 1
+#define CPO_REGISTER_02 2
+#define CPO_REGISTER_03 3
+#define CPO_REGISTER_04 4
+#define CPO_REGISTER_05 5
+#define CPO_REGISTER_06 6
+#define CPO_REGISTER_07 7
+#define CPO_REGISTER_08 8
+#define CPO_REGISTER_09 9
+#define CPO_REGISTER_10 10
+#define CPO_REGISTER_11 11
+#define CPO_REGISTER_12 12
+#define CPO_REGISTER_13 13
+#define CPO_REGISTER_14 14
+#define CPO_REGISTER_15 15
+#define CPO_REGISTER_16 16
+#define CPO_REGISTER_17 17
+#define CPO_REGISTER_18 18
+#define CPO_REGISTER_19 19
+#define CPO_REGISTER_20 20
+#define CPO_REGISTER_21 21
+#define CPO_REGISTER_22 22
+#define CPO_REGISTER_23 23
+#define CPO_REGISTER_24 24
+#define CPO_REGISTER_25 25
+#define CPO_REGISTER_26 26
+#define CPO_REGISTER_27 27
+#define CPO_REGISTER_28 28
+#define CPO_REGISTER_29 29
+#define CPO_REGISTER_30 30
+#define CPO_REGISTER_31 31
typedef struct TCState TCState;
--
2.7.4
next prev parent reply other threads:[~2019-01-18 17:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 01/12] target/mips: Move comment containing summary of CP0 registers Aleksandar Markovic
2019-01-18 16:59 ` Aleksandar Markovic [this message]
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 03/12] target/mips: Use preprocessor constants for 32 major " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 04/12] target/mips: Add fields for SAARI and SAAR " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 06/12] target/mips: Add field and R/W access to ITU control register ICR0 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers Aleksandar Markovic
2019-02-14 18:40 ` Peter Maydell
2019-02-14 18:58 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 08/12] target/mips: Update ITU to handle bus errors Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 09/12] target/mips: Amend preprocessor constants for CP0 registers Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 11/12] target/mips: Rename 'rn' to 'register_name' Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers Aleksandar Markovic
2020-11-14 18:23 ` Philippe Mathieu-Daudé
2020-12-12 10:19 ` Fredrik Noring
2019-01-21 19:19 ` [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Peter Maydell
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