From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PULL v2 04/12] target/mips: Add fields for SAARI and SAAR CP0 registers
Date: Fri, 18 Jan 2019 17:59:37 +0100 [thread overview]
Message-ID: <1547830785-7079-5-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1547830785-7079-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Yongbok Kim <yongbok.kim@mips.com>
Add fields for SAARI and SAAR CP0 registers.
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 10 ++++++++--
target/mips/machine.c | 6 ++++--
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index b095422..1c2c682 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -164,8 +164,8 @@ typedef struct mips_def_t mips_def_t;
* 3 BadInstrX
* 4 GuestCtl1 GuestCtl0Ext
* 5 GuestCtl2
- * 6 GuestCtl3
- * 7
+ * 6 SAARI GuestCtl3
+ * 7 SAAR
*
*
* Register 12 Register 13 Register 14 Register 15
@@ -546,6 +546,12 @@ struct CPUMIPSState {
* CP0 Register 9
*/
int32_t CP0_Count;
+ uint32_t CP0_SAARI;
+#define CP0SAARI_TARGET 0 /* 5..0 */
+ uint64_t CP0_SAAR[2];
+#define CP0SAAR_BASE 12 /* 43..12 */
+#define CP0SAAR_SIZE 1 /* 5..1 */
+#define CP0SAAR_EN 0
/*
* CP0 Register 10
*/
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 704e9c0..111d7c3 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -214,8 +214,8 @@ const VMStateDescription vmstate_tlb = {
const VMStateDescription vmstate_mips_cpu = {
.name = "cpu",
- .version_id = 15,
- .minimum_version_id = 15,
+ .version_id = 16,
+ .minimum_version_id = 16,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
/* Active TC */
@@ -274,6 +274,8 @@ const VMStateDescription vmstate_mips_cpu = {
VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
VMSTATE_INT32(env.CP0_Count, MIPSCPU),
+ VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
+ VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
VMSTATE_INT32(env.CP0_Status, MIPSCPU),
--
2.7.4
next prev parent reply other threads:[~2019-01-18 17:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-18 16:59 [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 01/12] target/mips: Move comment containing summary of CP0 registers Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 02/12] target/mips: Add preprocessor constants for 32 major " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 03/12] target/mips: Use " Aleksandar Markovic
2019-01-18 16:59 ` Aleksandar Markovic [this message]
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 05/12] target/mips: Provide R/W access to SAARI and SAAR " Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 06/12] target/mips: Add field and R/W access to ITU control register ICR0 Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 07/12] target/mips: Update ITU to utilize SAARI and SAAR CP0 registers Aleksandar Markovic
2019-02-14 18:40 ` Peter Maydell
2019-02-14 18:58 ` Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 08/12] target/mips: Update ITU to handle bus errors Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 09/12] target/mips: Amend preprocessor constants for CP0 registers Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 10/12] target/mips: Add CP0 register MemoryMapID Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 11/12] target/mips: Rename 'rn' to 'register_name' Aleksandar Markovic
2019-01-18 16:59 ` [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers Aleksandar Markovic
2020-11-14 18:23 ` Philippe Mathieu-Daudé
2020-12-12 10:19 ` Fredrik Noring
2019-01-21 19:19 ` [Qemu-devel] [PULL v2 00/12] MIPS queue for January 17, 2019 - v2 Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1547830785-7079-5-git-send-email-aleksandar.markovic@rt-rk.com \
--to=aleksandar.markovic@rt-rk.com \
--cc=amarkovic@wavecomp.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).