From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:59462) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gqj6x-00058Q-9A for qemu-devel@nongnu.org; Mon, 04 Feb 2019 13:36:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gqj6u-0003ZS-Pi for qemu-devel@nongnu.org; Mon, 04 Feb 2019 13:36:51 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:38893) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gqj6u-0003YJ-Hn for qemu-devel@nongnu.org; Mon, 04 Feb 2019 13:36:48 -0500 Received: by mail-wr1-x42e.google.com with SMTP id v13so961367wrw.5 for ; Mon, 04 Feb 2019 10:36:48 -0800 (PST) Received: from 640k.lan ([93.56.166.5]) by smtp.gmail.com with ESMTPSA id s132sm8836236wmf.28.2019.02.04.10.36.46 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Feb 2019 10:36:46 -0800 (PST) Sender: Paolo Bonzini From: Paolo Bonzini Date: Mon, 4 Feb 2019 19:35:28 +0100 Message-Id: <1549305379-51117-27-git-send-email-pbonzini@redhat.com> In-Reply-To: <1549305379-51117-1-git-send-email-pbonzini@redhat.com> References: <1549305379-51117-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 26/77] target-i386: hvf: remove MPX support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org MPX support is being phased out by Intel and actually I am not sure that OS X has ever enabled it in XCR0. Drop it from the Hypervisor.framework acceleration. Signed-off-by: Paolo Bonzini --- target/i386/hvf/x86_cpuid.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/target/i386/hvf/x86_cpuid.c b/target/i386/hvf/x86_cpuid.c index 9874a46..4d957fe 100644 --- a/target/i386/hvf/x86_cpuid.c +++ b/target/i386/hvf/x86_cpuid.c @@ -38,16 +38,6 @@ static uint64_t xgetbv(uint32_t xcr) return (((uint64_t)edx) << 32) | eax; } -static bool vmx_mpx_supported() -{ - uint64_t cap_exit, cap_entry; - - hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &cap_entry); - hv_vmx_read_capability(HV_VMX_CAP_EXIT, &cap_exit); - - return ((cap_exit & (1 << 23)) && (cap_entry & (1 << 16))); -} - uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, int reg) { @@ -92,11 +82,8 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512DQ | CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL | - CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_MPX; + CPUID_7_0_EBX_INVPCID; - if (!vmx_mpx_supported()) { - ebx &= ~CPUID_7_0_EBX_MPX; - } hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap); if (!(cap & CPU_BASED2_INVPCID)) { ebx &= ~CPUID_7_0_EBX_INVPCID; @@ -119,9 +106,6 @@ uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK); eax &= supp_xcr0; - if (!vmx_mpx_supported()) { - eax &= ~(XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK); - } } else if (idx == 1) { hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &cap); eax &= CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1; -- 1.8.3.1