From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:56848) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gz3Dh-0000SK-UE for qemu-devel@nongnu.org; Wed, 27 Feb 2019 12:42:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gz3Dd-0001H1-S9 for qemu-devel@nongnu.org; Wed, 27 Feb 2019 12:42:13 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:53596 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gz3DO-00004x-1x for qemu-devel@nongnu.org; Wed, 27 Feb 2019 12:42:01 -0500 From: Mateja Marjanovic Date: Wed, 27 Feb 2019 18:40:14 +0100 Message-Id: <1551289217-10072-2-git-send-email-mateja.marjanovic@rt-rk.com> In-Reply-To: <1551289217-10072-1-git-send-email-mateja.marjanovic@rt-rk.com> References: <1551289217-10072-1-git-send-email-mateja.marjanovic@rt-rk.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 1/4] target/mips: Optimize support for MSA instructions ILVEV. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net, amarkovic@wavecomp.com, arikalo@wavecomp.com From: Mateja Marjanovic Optimize support for MSA instructions ILVEV.B, ILVEV.H, ILVEV.W, and ILVEV.D. Optimization is done by eliminating loops, and explicitly assigning desired values to individual data elements. Performance measurement is done by executing the instructions large number of times on a computer with Intel Core i7-3770 CPU @ 3.40GHz=C3=978. Measured time before optimization: ILVEV.B: 119.02 ms ILVEV.H: 94.16 ms ILVEV.W: 120.97 ms ILVEV.D: 42.99 ms Measured time after optimization: ILVEV.B: 61.81 ms ILVEV.H: 42.78 ms ILVEV.W: 39.47 ms ILVEV.D: 39.11 ms Signed-off-by: Mateja Marjanovic --- target/mips/msa_helper.c | 60 +++++++++++++++++++++++++++++++++++++++++-= ------ 1 file changed, 52 insertions(+), 8 deletions(-) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index c74e3cd..4e6584e 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -1198,14 +1198,6 @@ MSA_FN_DF(ilvl_df) MSA_FN_DF(ilvr_df) #undef MSA_DO =20 -#define MSA_DO(DF) \ - do { \ - pwx->DF[2*i] =3D pwt->DF[2*i]; \ - pwx->DF[2*i+1] =3D pws->DF[2*i]; \ - } while (0) -MSA_FN_DF(ilvev_df) -#undef MSA_DO - #define MSA_DO(DF) \ do { \ pwx->DF[2*i] =3D pwt->DF[2*i+1]; \ @@ -1230,6 +1222,58 @@ MSA_FN_DF(vshf_df) #undef MSA_LOOP_COND #undef MSA_FN_DF =20 + +void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, + uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + switch (df) { + case DF_BYTE: + pwd->b[0] =3D pwt->b[0]; + pwd->b[1] =3D pws->b[0]; + pwd->b[2] =3D pwt->b[2]; + pwd->b[3] =3D pws->b[2]; + pwd->b[4] =3D pwt->b[4]; + pwd->b[5] =3D pws->b[4]; + pwd->b[6] =3D pwt->b[6]; + pwd->b[7] =3D pws->b[6]; + pwd->b[8] =3D pwt->b[8]; + pwd->b[9] =3D pws->b[8]; + pwd->b[10] =3D pwt->b[10]; + pwd->b[11] =3D pws->b[10]; + pwd->b[12] =3D pwt->b[12]; + pwd->b[13] =3D pws->b[12]; + pwd->b[14] =3D pwt->b[14]; + pwd->b[15] =3D pws->b[14]; + break; + case DF_HALF: + pwd->h[0] =3D pwt->h[0]; + pwd->h[1] =3D pws->h[0]; + pwd->h[2] =3D pwt->h[2]; + pwd->h[3] =3D pws->h[2]; + pwd->h[4] =3D pwt->h[4]; + pwd->h[5] =3D pws->h[4]; + pwd->h[6] =3D pwt->h[6]; + pwd->h[7] =3D pws->h[6]; + break; + case DF_WORD: + pwd->w[0] =3D pwt->w[0]; + pwd->w[1] =3D pws->w[0]; + pwd->w[2] =3D pwt->w[2]; + pwd->w[3] =3D pws->w[2]; + break; + case DF_DOUBLE: + pwd->d[0] =3D pwt->d[0]; + pwd->d[1] =3D pws->d[0]; + break; + default: + assert(0); + } +} + void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t ws, uint32_t n) { --=20 2.7.4