* [Qemu-devel] [PATCH v5 01/16] tcg/ppc: Introduce Altivec registers
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec Aleksandar Markovic
` (15 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Altivec (in all its versions) supports 32 128-bit vector registers,
whase names are by convention v0, v1,..., and v32.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 11 +++++-
tcg/ppc/tcg-target.inc.c | 88 ++++++++++++++++++++++++++++++------------------
2 files changed, 65 insertions(+), 34 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 7627fb6..690fa74 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -31,7 +31,7 @@
# define TCG_TARGET_REG_BITS 32
#endif
-#define TCG_TARGET_NB_REGS 32
+#define TCG_TARGET_NB_REGS 64
#define TCG_TARGET_INSN_UNIT_SIZE 4
#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
@@ -45,6 +45,15 @@ typedef enum {
TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
+ TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
+ TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
+ TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
+ TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
+ TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
+ TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
+ TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
+ TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
+
TCG_REG_CALL_STACK = TCG_REG_R1,
TCG_AREG0 = TCG_REG_R27
} TCGReg;
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 852b894..8e1bba7 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -42,6 +42,9 @@
# define TCG_REG_TMP1 TCG_REG_R12
#endif
+#define TCG_VEC_TMP1 TCG_REG_V0
+#define TCG_VEC_TMP2 TCG_REG_V1
+
#define TCG_REG_TB TCG_REG_R31
#define USE_REG_TB (TCG_TARGET_REG_BITS == 64)
@@ -72,39 +75,15 @@ bool have_isa_3_00;
#endif
#ifdef CONFIG_DEBUG_TCG
-static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
- "r0",
- "r1",
- "r2",
- "r3",
- "r4",
- "r5",
- "r6",
- "r7",
- "r8",
- "r9",
- "r10",
- "r11",
- "r12",
- "r13",
- "r14",
- "r15",
- "r16",
- "r17",
- "r18",
- "r19",
- "r20",
- "r21",
- "r22",
- "r23",
- "r24",
- "r25",
- "r26",
- "r27",
- "r28",
- "r29",
- "r30",
- "r31"
+static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = {
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
+ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
};
#endif
@@ -139,6 +118,26 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R5,
TCG_REG_R4,
TCG_REG_R3,
+
+ /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
+ TCG_REG_V2, /* call clobbered, vectors */
+ TCG_REG_V3,
+ TCG_REG_V4,
+ TCG_REG_V5,
+ TCG_REG_V6,
+ TCG_REG_V7,
+ TCG_REG_V8,
+ TCG_REG_V9,
+ TCG_REG_V10,
+ TCG_REG_V11,
+ TCG_REG_V12,
+ TCG_REG_V13,
+ TCG_REG_V14,
+ TCG_REG_V15,
+ TCG_REG_V16,
+ TCG_REG_V17,
+ TCG_REG_V18,
+ TCG_REG_V19,
};
static const int tcg_target_call_iarg_regs[] = {
@@ -2808,6 +2807,27 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18);
+ tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19);
+
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
@@ -2818,6 +2838,8 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
#endif
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
+ tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2);
if (USE_REG_TB) {
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */
}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 01/16] tcg/ppc: Introduce Altivec registers Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 03/16] tcg/ppc: Introduce macro VX4() Aleksandar Markovic
` (14 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Detect during initialization if the emulated CPU supports Altivec,
and store the result in the flag have_isa_altivec. The definition
of Altivec SIMD instructions set evolved over time. Different
generations of Altivec will be distinguished by other flags in TCG,
and they are currently have_isa_2_06 and have_isa_3_00.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 25 +++++++++++++++++++++++++
tcg/ppc/tcg-target.inc.c | 8 ++++++++
2 files changed, 33 insertions(+)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 690fa74..f6283f4 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -58,6 +58,7 @@ typedef enum {
TCG_AREG0 = TCG_REG_R27
} TCGReg;
+extern bool have_isa_altivec;
extern bool have_isa_2_06;
extern bool have_isa_3_00;
@@ -135,6 +136,30 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_mulsh_i64 1
#endif
+/*
+ * While technically Altivec could support V64, it has no 64-bit store
+ * instruction and substituting two 32-bit stores makes the generated
+ * code quite large.
+ */
+#define TCG_TARGET_HAS_v64 0
+#define TCG_TARGET_HAS_v128 have_isa_altivec
+#define TCG_TARGET_HAS_v256 0
+
+#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_abs_vec 0
+#define TCG_TARGET_HAS_shi_vec 0
+#define TCG_TARGET_HAS_shs_vec 0
+#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_cmpsel_vec 0
+
void flush_icache_range(uintptr_t start, uintptr_t stop);
void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 8e1bba7..26892de 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -64,6 +64,7 @@
static tcg_insn_unit *tb_ret_addr;
+bool have_isa_altivec;
bool have_isa_2_06;
bool have_isa_3_00;
@@ -2781,6 +2782,9 @@ static void tcg_target_init(TCGContext *s)
unsigned long hwcap = qemu_getauxval(AT_HWCAP);
unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2);
+ if (hwcap & PPC_FEATURE_HAS_ALTIVEC) {
+ have_isa_altivec = true;
+ }
if (hwcap & PPC_FEATURE_ARCH_2_06) {
have_isa_2_06 = true;
}
@@ -2792,6 +2796,10 @@ static void tcg_target_init(TCGContext *s)
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
+ if (have_isa_altivec) {
+ tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
+ tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
+ }
tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 03/16] tcg/ppc: Introduce macro VX4()
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 01/16] tcg/ppc: Introduce Altivec registers Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 02/16] tcg/ppc: Introduce flag have_isa_altivec Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 04/16] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC() Aleksandar Markovic
` (13 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Introduce macro VX4() used for coding/decoding Altivec instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 26892de..8c67c99 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -320,6 +320,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define XO31(opc) (OPCD(31)|((opc)<<1))
#define XO58(opc) (OPCD(58)|(opc))
#define XO62(opc) (OPCD(62)|(opc))
+#define VX4(opc) (OPCD(4)|(opc))
#define B OPCD( 18)
#define BC OPCD( 16)
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 04/16] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (2 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 03/16] tcg/ppc: Introduce macro VX4() Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 05/16] tcg/ppc: Add support for load/store/logic/comparison Aleksandar Markovic
` (12 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Introduce macros VRT(), VRA(), VRB(), VRC() used for coding/decoding
elements of Altivec instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.inc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 8c67c99..0fe96bf 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,6 +474,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define MB64(b) ((b)<<5)
#define FXM(b) (1 << (19 - (b)))
+#define VRT(r) (((r) & 31) << 21)
+#define VRA(r) (((r) & 31) << 16)
+#define VRB(r) (((r) & 31) << 11)
+#define VRC(r) (((r) & 31) << 6)
+
#define LK 1
#define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 05/16] tcg/ppc: Add support for load/store/logic/comparison
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (3 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 04/16] tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC() Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 06/16] tcg/ppc: Add support for vector maximum/minimum Aleksandar Markovic
` (11 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Add various bits and peaces related mostly to load and store
operations. In that context, logic, compare, and splat Altivec
instructions are used, and, therefore, the support for emitting
them is included in this patch too.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 6 +-
tcg/ppc/tcg-target.inc.c | 506 ++++++++++++++++++++++++++++++++++++++++++++---
2 files changed, 484 insertions(+), 28 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index f6283f4..b66a808 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -145,15 +145,15 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_v128 have_isa_altivec
#define TCG_TARGET_HAS_v256 0
-#define TCG_TARGET_HAS_andc_vec 0
+#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 0
-#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 0
-#define TCG_TARGET_HAS_cmp_vec 0
+#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 0fe96bf..d3e4557 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -233,6 +233,10 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
break;
+ case 'v':
+ ct->ct |= TCG_CT_REG;
+ ct->u.regs = 0xffffffff00000000ull;
+ break;
case 'L': /* qemu_ld constraint */
ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff;
@@ -462,6 +466,39 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define NOP ORI /* ori 0,0,0 */
+#define LVX XO31(103)
+#define LVEBX XO31(7)
+#define LVEHX XO31(39)
+#define LVEWX XO31(71)
+
+#define STVX XO31(231)
+#define STVEWX XO31(199)
+
+#define VCMPEQUB VX4(6)
+#define VCMPEQUH VX4(70)
+#define VCMPEQUW VX4(134)
+#define VCMPGTSB VX4(774)
+#define VCMPGTSH VX4(838)
+#define VCMPGTSW VX4(902)
+#define VCMPGTUB VX4(518)
+#define VCMPGTUH VX4(582)
+#define VCMPGTUW VX4(646)
+
+#define VAND VX4(1028)
+#define VANDC VX4(1092)
+#define VNOR VX4(1284)
+#define VOR VX4(1156)
+#define VXOR VX4(1220)
+
+#define VSPLTB VX4(524)
+#define VSPLTH VX4(588)
+#define VSPLTW VX4(652)
+#define VSPLTISB VX4(780)
+#define VSPLTISH VX4(844)
+#define VSPLTISW VX4(908)
+
+#define VSLDOI VX4(44)
+
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
@@ -535,6 +572,8 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
tcg_insn_unit *target;
+ int16_t lo;
+ int32_t hi;
value += addend;
target = (tcg_insn_unit *)value;
@@ -556,6 +595,20 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
}
*code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
break;
+ case R_PPC_ADDR32:
+ /*
+ * We are abusing this relocation type. Again, this points to
+ * a pair of insns, lis + load. This is an absolute address
+ * relocation for PPC32 so the lis cannot be removed.
+ */
+ lo = value;
+ hi = value - lo;
+ if (hi + lo != value) {
+ return false;
+ }
+ code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
+ code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
+ break;
default:
g_assert_not_reached();
}
@@ -567,9 +620,29 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
- if (ret != arg) {
- tcg_out32(s, OR | SAB(arg, ret, arg));
+ if (ret == arg) {
+ return true;
+ }
+ switch (type) {
+ case TCG_TYPE_I64:
+ tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
+ /* fallthru */
+ case TCG_TYPE_I32:
+ if (ret < 32 && arg < 32) {
+ tcg_out32(s, OR | SAB(arg, ret, arg));
+ break;
+ } else if (ret < 32 || arg < 32) {
+ /* Altivec does not support vector/integer moves. */
+ return false;
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 32 && arg >= 32);
+ tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg));
+ break;
+ default:
+ g_assert_not_reached();
}
return true;
}
@@ -718,10 +791,76 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
}
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
- tcg_target_long arg)
+static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long val)
+{
+ uint32_t load_insn;
+ int rel, low;
+ intptr_t add;
+
+ low = (int8_t)val;
+ if (low >= -16 && low < 16) {
+ if (val == (tcg_target_long)dup_const(MO_8, low)) {
+ tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16));
+ return;
+ }
+ if (val == (tcg_target_long)dup_const(MO_16, low)) {
+ tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16));
+ return;
+ }
+ if (val == (tcg_target_long)dup_const(MO_32, low)) {
+ tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16));
+ return;
+ }
+ }
+
+ /*
+ * Otherwise we must load the value from the constant pool.
+ */
+ if (USE_REG_TB) {
+ rel = R_PPC_ADDR16;
+ add = -(intptr_t)s->code_gen_ptr;
+ } else {
+ rel = R_PPC_ADDR32;
+ add = 0;
+ }
+
+ load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
+ if (TCG_TARGET_REG_BITS == 64) {
+ new_pool_l2(s, rel, s->code_ptr, add, val, val);
+ } else {
+ new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+ }
+
+ if (USE_REG_TB) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0));
+ load_insn |= RA(TCG_REG_TB);
+ } else {
+ tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0));
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0));
+ }
+ tcg_out32(s, load_insn);
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
+ tcg_target_long arg)
{
- tcg_out_movi_int(s, type, ret, arg, false);
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ tcg_debug_assert(ret < 32);
+ tcg_out_movi_int(s, type, ret, arg, false);
+ break;
+
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 32);
+ tcg_out_dupi_vec(s, type, ret, arg);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
}
static bool mask_operand(uint32_t c, int *mb, int *me)
@@ -874,7 +1013,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
}
/* For unaligned, or very large offsets, use the indexed form. */
- if (offset & align || offset != (int32_t)offset) {
+ if (offset & align || offset != (int32_t)offset || opi == 0) {
if (rs == base) {
rs = TCG_REG_R0;
}
@@ -905,32 +1044,96 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
}
}
-static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_vsldoi(TCGContext *s, TCGReg ret,
+ TCGReg va, TCGReg vb, int shb)
{
- int opi, opx;
+ tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6));
+}
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
- if (type == TCG_TYPE_I32) {
- opi = LWZ, opx = LWZX;
- } else {
- opi = LD, opx = LDX;
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
+ TCGReg base, intptr_t offset)
+{
+ int shift;
+
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (ret < 32) {
+ tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
+ break;
+ }
+ assert((offset & 3) == 0);
+ tcg_out_mem_long(s, 0, LVEWX, ret & 31, base, offset);
+ shift = (offset - 4) & 0xc;
+ if (shift) {
+ tcg_out_vsldoi(s, ret, ret, ret, shift);
+ }
+ break;
+ case TCG_TYPE_I64:
+ if (ret < 32) {
+ tcg_out_mem_long(s, LD, LDX, ret, base, offset);
+ break;
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ tcg_debug_assert(ret >= 32);
+ assert((offset & 7) == 0);
+ tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset & -16);
+ if (offset & 8) {
+ tcg_out_vsldoi(s, ret, ret, ret, 8);
+ }
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(ret >= 32);
+ assert((offset & 15) == 0);
+ tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset);
+ break;
+ default:
+ g_assert_not_reached();
}
- tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
}
-static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
- TCGReg arg1, intptr_t arg2)
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+ TCGReg base, intptr_t offset)
{
- int opi, opx;
+ int shift;
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
- if (type == TCG_TYPE_I32) {
- opi = STW, opx = STWX;
- } else {
- opi = STD, opx = STDX;
+ switch (type) {
+ case TCG_TYPE_I32:
+ if (arg < 32) {
+ tcg_out_mem_long(s, STW, STWX, arg, base, offset);
+ break;
+ }
+ assert((offset & 3) == 0);
+ shift = (offset - 4) & 0xc;
+ if (shift) {
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift);
+ arg = TCG_VEC_TMP1;
+ }
+ tcg_out_mem_long(s, 0, STVEWX, arg & 31, base, offset);
+ break;
+ case TCG_TYPE_I64:
+ if (arg < 32) {
+ tcg_out_mem_long(s, STD, STDX, arg, base, offset);
+ break;
+ }
+ /* fallthru */
+ case TCG_TYPE_V64:
+ tcg_debug_assert(arg >= 32);
+ assert((offset & 7) == 0);
+ if (offset & 8) {
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
+ arg = TCG_VEC_TMP1;
+ }
+ tcg_out_mem_long(s, 0, STVEWX, arg & 31, base, offset);
+ tcg_out_mem_long(s, 0, STVEWX, arg & 31, base, offset + 4);
+ break;
+ case TCG_TYPE_V128:
+ tcg_debug_assert(arg >= 32);
+ tcg_out_mem_long(s, 0, STVX, arg & 31, base, offset);
+ break;
+ default:
+ g_assert_not_reached();
}
- tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
}
static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
@@ -2606,6 +2809,241 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
}
}
+int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
+{
+ switch (opc) {
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_not_vec:
+ return 1;
+ case INDEX_op_cmp_vec:
+ return vece <= MO_32 ? -1 : 0;
+ default:
+ return 0;
+ }
+}
+
+static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg dst, TCGReg src)
+{
+ tcg_debug_assert(dst >= 32);
+ tcg_debug_assert(src >= 32);
+
+ /*
+ * Recall we use (or emulate) VSX integer loads, so the integer is
+ * right justified within the left (zero-index) double-word.
+ */
+ switch (vece) {
+ case MO_8:
+ tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16));
+ break;
+ case MO_16:
+ tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16));
+ break;
+ case MO_32:
+ tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
+ break;
+ case MO_64:
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
+ tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
+ TCGReg out, TCGReg base, intptr_t offset)
+{
+ int elt;
+
+ tcg_debug_assert(out >= 32);
+ out &= 31;
+ switch (vece) {
+ case MO_8:
+ tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
+ elt = extract32(offset, 0, 4);
+#ifndef HOST_WORDS_BIGENDIAN
+ elt ^= 15;
+#endif
+ tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16));
+ break;
+ case MO_16:
+ assert((offset & 1) == 0);
+ tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
+ elt = extract32(offset, 1, 3);
+#ifndef HOST_WORDS_BIGENDIAN
+ elt ^= 7;
+#endif
+ tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
+ break;
+ case MO_32:
+ assert((offset & 3) == 0);
+ tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
+ elt = extract32(offset, 2, 2);
+#ifndef HOST_WORDS_BIGENDIAN
+ elt ^= 3;
+#endif
+ tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
+ break;
+ case MO_64:
+ assert((offset & 7) == 0);
+ tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
+ elt = extract32(offset, 3, 1);
+#ifndef HOST_WORDS_BIGENDIAN
+ elt = !elt;
+#endif
+ if (elt) {
+ tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8);
+ } else {
+ tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8);
+ }
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ return true;
+}
+
+static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
+ unsigned vecl, unsigned vece,
+ const TCGArg *args, const int *const_args)
+{
+ static const uint32_t
+ eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
+ gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
+ gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 };
+
+ TCGType type = vecl + TCG_TYPE_V64;
+ TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
+ uint32_t insn;
+
+ switch (opc) {
+ case INDEX_op_ld_vec:
+ tcg_out_ld(s, type, a0, a1, a2);
+ return;
+ case INDEX_op_st_vec:
+ tcg_out_st(s, type, a0, a1, a2);
+ return;
+ case INDEX_op_dupm_vec:
+ tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
+ return;
+
+ case INDEX_op_and_vec:
+ insn = VAND;
+ break;
+ case INDEX_op_or_vec:
+ insn = VOR;
+ break;
+ case INDEX_op_xor_vec:
+ insn = VXOR;
+ break;
+ case INDEX_op_andc_vec:
+ insn = VANDC;
+ break;
+ case INDEX_op_not_vec:
+ insn = VNOR;
+ a2 = a1;
+ break;
+
+ case INDEX_op_cmp_vec:
+ switch (args[3]) {
+ case TCG_COND_EQ:
+ insn = eq_op[vece];
+ break;
+ case TCG_COND_GT:
+ insn = gts_op[vece];
+ break;
+ case TCG_COND_GTU:
+ insn = gtu_op[vece];
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ break;
+
+ case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
+ case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
+ case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
+ default:
+ g_assert_not_reached();
+ }
+
+ tcg_debug_assert(insn != 0);
+ tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
+}
+
+static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2, TCGCond cond)
+{
+ bool need_swap = false, need_inv = false;
+
+ tcg_debug_assert(vece <= MO_32);
+
+ switch (cond) {
+ case TCG_COND_EQ:
+ case TCG_COND_GT:
+ case TCG_COND_GTU:
+ break;
+ case TCG_COND_NE:
+ case TCG_COND_LE:
+ case TCG_COND_LEU:
+ need_inv = true;
+ break;
+ case TCG_COND_LT:
+ case TCG_COND_LTU:
+ need_swap = true;
+ break;
+ case TCG_COND_GE:
+ case TCG_COND_GEU:
+ need_swap = need_inv = true;
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ if (need_inv) {
+ cond = tcg_invert_cond(cond);
+ }
+ if (need_swap) {
+ TCGv_vec t1;
+ t1 = v1, v1 = v2, v2 = t1;
+ cond = tcg_swap_cond(cond);
+ }
+
+ vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond);
+
+ if (need_inv) {
+ tcg_gen_not_vec(vece, v0, v0);
+ }
+}
+
+void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
+ TCGArg a0, ...)
+{
+ va_list va;
+ TCGv_vec v0, v1, v2;
+
+ va_start(va, a0);
+ v0 = temp_tcgv_vec(arg_temp(a0));
+ v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+
+ switch (opc) {
+ case INDEX_op_cmp_vec:
+ expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
+ break;
+ default:
+ g_assert_not_reached();
+ }
+ va_end(va);
+}
+
static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
{
static const TCGTargetOpDef r = { .args_ct_str = { "r" } };
@@ -2643,6 +3081,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
= { .args_ct_str = { "r", "r", "r", "r", "rI", "rZM" } };
static const TCGTargetOpDef sub2
= { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
+ static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
+ static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
+ static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
switch (op) {
case INDEX_op_goto_ptr:
@@ -2778,6 +3219,21 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
return (TCG_TARGET_REG_BITS == 64 ? &S_S
: TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
+ case INDEX_op_and_vec:
+ case INDEX_op_or_vec:
+ case INDEX_op_xor_vec:
+ case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_cmp_vec:
+ return &v_v_v;
+ case INDEX_op_not_vec:
+ case INDEX_op_dup_vec:
+ return &v_v;
+ case INDEX_op_ld_vec:
+ case INDEX_op_st_vec:
+ case INDEX_op_dupm_vec:
+ return &v_r;
+
default:
return NULL;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 06/16] tcg/ppc: Add support for vector maximum/minimum
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (4 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 05/16] tcg/ppc: Add support for load/store/logic/comparison Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 07/16] tcg/ppc: Add support for vector add/subtract Aleksandar Markovic
` (10 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Add support for vector maximum/minimum using Altivec instructions
VMAXSB, VMAXSH, VMAXSW, VMAXUB, VMAXUH, VMAXUW, and
VMINSB, VMINSH, VMINSW, VMINUB, VMINUH, VMINUW.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 40 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index b66a808..a86ed57 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -156,7 +156,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 0
-#define TCG_TARGET_HAS_minmax_vec 0
+#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index d3e4557..e1142e7 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,6 +474,19 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VMAXSB VX4(258)
+#define VMAXSH VX4(322)
+#define VMAXSW VX4(386)
+#define VMAXUB VX4(2)
+#define VMAXUH VX4(66)
+#define VMAXUW VX4(130)
+#define VMINSB VX4(770)
+#define VMINSH VX4(834)
+#define VMINSW VX4(898)
+#define VMINUB VX4(514)
+#define VMINUH VX4(578)
+#define VMINUW VX4(642)
+
#define VCMPEQUB VX4(6)
#define VCMPEQUH VX4(70)
#define VCMPEQUW VX4(134)
@@ -2818,6 +2831,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
return 1;
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
+ return vece <= MO_32;
case INDEX_op_cmp_vec:
return vece <= MO_32 ? -1 : 0;
default:
@@ -2916,7 +2934,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const uint32_t
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
- gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 };
+ gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
+ umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
+ smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
+ umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
+ smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -2933,6 +2955,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
return;
+ case INDEX_op_smin_vec:
+ insn = smin_op[vece];
+ break;
+ case INDEX_op_umin_vec:
+ insn = umin_op[vece];
+ break;
+ case INDEX_op_smax_vec:
+ insn = smax_op[vece];
+ break;
+ case INDEX_op_umax_vec:
+ insn = umax_op[vece];
+ break;
case INDEX_op_and_vec:
insn = VAND;
break;
@@ -3225,6 +3259,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
case INDEX_op_cmp_vec:
+ case INDEX_op_smax_vec:
+ case INDEX_op_smin_vec:
+ case INDEX_op_umax_vec:
+ case INDEX_op_umin_vec:
return &v_v_v;
case INDEX_op_not_vec:
case INDEX_op_dup_vec:
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 07/16] tcg/ppc: Add support for vector add/subtract
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (5 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 06/16] tcg/ppc: Add support for vector maximum/minimum Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 08/16] tcg/ppc: Add support for vector saturated add/subtract Aleksandar Markovic
` (9 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Add support for vector add/subtract using Altivec instructions:
VADDUBM, VADDUHM, VADDUWM, VSUBUBM, VSUBUHM, VSUBUWM.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.inc.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index e1142e7..e254fa4 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,6 +474,14 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VADDUBM VX4(0)
+#define VADDUHM VX4(64)
+#define VADDUWM VX4(128)
+
+#define VSUBUBM VX4(1024)
+#define VSUBUHM VX4(1088)
+#define VSUBUWM VX4(1152)
+
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
@@ -2831,6 +2839,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
return 1;
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
@@ -2932,6 +2942,8 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
static const uint32_t
+ add_op[4] = { VADDUBM, VADDUHM, VADDUWM, 0 },
+ sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, 0 },
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
@@ -2955,6 +2967,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
return;
+ case INDEX_op_add_vec:
+ insn = add_op[vece];
+ break;
+ case INDEX_op_sub_vec:
+ insn = sub_op[vece];
+ break;
case INDEX_op_smin_vec:
insn = smin_op[vece];
break;
@@ -3253,6 +3271,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
return (TCG_TARGET_REG_BITS == 64 ? &S_S
: TARGET_LONG_BITS == 32 ? &S_S_S : &S_S_S_S);
+ case INDEX_op_add_vec:
+ case INDEX_op_sub_vec:
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 08/16] tcg/ppc: Add support for vector saturated add/subtract
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (6 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 07/16] tcg/ppc: Add support for vector add/subtract Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 09/16] tcg/ppc: Prepare case for vector multiply Aleksandar Markovic
` (8 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Add support for vector saturated add/subtract using Altivec
instructions:
VADDSBS, VADDSHS, VADDSWS, VADDUBS, VADDUHS, VADDUWS, and
VSUBSBS, VSUBSHS, VSUBSWS, VSUBUBS, VSUBUHS, VSUBUWS.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index a86ed57..368c250 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -155,7 +155,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_shv_vec 0
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
-#define TCG_TARGET_HAS_sat_vec 0
+#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index e254fa4..108882f 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -474,12 +474,24 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define VADDSBS VX4(768)
+#define VADDUBS VX4(512)
#define VADDUBM VX4(0)
+#define VADDSHS VX4(832)
+#define VADDUHS VX4(576)
#define VADDUHM VX4(64)
+#define VADDSWS VX4(896)
+#define VADDUWS VX4(640)
#define VADDUWM VX4(128)
+#define VSUBSBS VX4(1792)
+#define VSUBUBS VX4(1536)
#define VSUBUBM VX4(1024)
+#define VSUBSHS VX4(1856)
+#define VSUBUHS VX4(1600)
#define VSUBUHM VX4(1088)
+#define VSUBSWS VX4(1920)
+#define VSUBUWS VX4(1664)
#define VSUBUWM VX4(1152)
#define VMAXSB VX4(258)
@@ -2845,6 +2857,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
return vece <= MO_32 ? -1 : 0;
@@ -2947,6 +2963,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
+ ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
+ usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
+ sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
+ ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
@@ -2973,6 +2993,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sub_vec:
insn = sub_op[vece];
break;
+ case INDEX_op_ssadd_vec:
+ insn = ssadd_op[vece];
+ break;
+ case INDEX_op_sssub_vec:
+ insn = sssub_op[vece];
+ break;
+ case INDEX_op_usadd_vec:
+ insn = usadd_op[vece];
+ break;
+ case INDEX_op_ussub_vec:
+ insn = ussub_op[vece];
+ break;
case INDEX_op_smin_vec:
insn = smin_op[vece];
break;
@@ -3279,6 +3311,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
case INDEX_op_cmp_vec:
+ case INDEX_op_ssadd_vec:
+ case INDEX_op_sssub_vec:
+ case INDEX_op_usadd_vec:
+ case INDEX_op_ussub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 09/16] tcg/ppc: Prepare case for vector multiply
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (7 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 08/16] tcg/ppc: Add support for vector saturated add/subtract Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 10/16] tcg/ppc: Add empty file tcg-target.opc.h Aleksandar Markovic
` (7 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
This line is just preparation for full vector multiply support
in some of subsequent patches.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.inc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 108882f..03a48c9 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -3305,6 +3305,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_and_vec:
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 10/16] tcg/ppc: Add empty file tcg-target.opc.h
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (8 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 09/16] tcg/ppc: Prepare case for vector multiply Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 11/16] tcg/ppc: Support vector shift by immediate Aleksandar Markovic
` (6 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
Add empty file tcg-target.opc.h to be used in future.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.opc.h | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 tcg/ppc/tcg-target.opc.h
diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h
new file mode 100644
index 0000000..4816a6c
--- /dev/null
+++ b/tcg/ppc/tcg-target.opc.h
@@ -0,0 +1,3 @@
+/* Target-specific opcodes for host vector expansion. These will be
+ emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ consider these to be UNSPEC with names. */
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 11/16] tcg/ppc: Support vector shift by immediate
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (9 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 10/16] tcg/ppc: Add empty file tcg-target.opc.h Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 12/16] tcg/ppc: Support vector multiply Aleksandar Markovic
` (5 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
For Altivec, this is done via vector shift by vector,
and loading the immediate into a register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++--
2 files changed, 57 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 368c250..766706f 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -152,7 +152,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
-#define TCG_TARGET_HAS_shv_vec 0
+#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_cmp_vec 1
#define TCG_TARGET_HAS_mul_vec 0
#define TCG_TARGET_HAS_sat_vec 1
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 03a48c9..3eb18cb 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -517,6 +517,16 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
+#define VSLB VX4(260)
+#define VSLH VX4(324)
+#define VSLW VX4(388)
+#define VSRB VX4(516)
+#define VSRH VX4(580)
+#define VSRW VX4(644)
+#define VSRAB VX4(772)
+#define VSRAH VX4(836)
+#define VSRAW VX4(900)
+
#define VAND VX4(1028)
#define VANDC VX4(1092)
#define VNOR VX4(1284)
@@ -2861,8 +2871,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
+ case INDEX_op_shli_vec:
+ case INDEX_op_shri_vec:
+ case INDEX_op_sari_vec:
return vece <= MO_32 ? -1 : 0;
default:
return 0;
@@ -2970,7 +2986,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
- smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 };
+ smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
+ shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
+ shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
+ sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -3017,6 +3036,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_umax_vec:
insn = umax_op[vece];
break;
+ case INDEX_op_shlv_vec:
+ insn = shlv_op[vece];
+ break;
+ case INDEX_op_shrv_vec:
+ insn = shrv_op[vece];
+ break;
+ case INDEX_op_sarv_vec:
+ insn = sarv_op[vece];
+ break;
case INDEX_op_and_vec:
insn = VAND;
break;
@@ -3061,6 +3089,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2));
}
+static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGArg imm, TCGOpcode opci)
+{
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+
+ /* Splat w/bytes for xxspltib. */
+ tcg_gen_dupi_vec(MO_8, t1, imm & ((8 << vece) - 1));
+ vec_gen_3(opci, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1));
+ tcg_temp_free_vec(t1);
+}
+
static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGv_vec v2, TCGCond cond)
{
@@ -3112,14 +3152,25 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
{
va_list va;
TCGv_vec v0, v1, v2;
+ TCGArg a2;
va_start(va, a0);
v0 = temp_tcgv_vec(arg_temp(a0));
v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
- v2 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg)));
+ a2 = va_arg(va, TCGArg);
switch (opc) {
+ case INDEX_op_shli_vec:
+ expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec);
+ break;
+ case INDEX_op_shri_vec:
+ expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec);
+ break;
+ case INDEX_op_sari_vec:
+ expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec);
+ break;
case INDEX_op_cmp_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
break;
default:
@@ -3320,6 +3371,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
return &v_v_v;
case INDEX_op_not_vec:
case INDEX_op_dup_vec:
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 12/16] tcg/ppc: Support vector multiply
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (10 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 11/16] tcg/ppc: Support vector shift by immediate Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 13/16] tcg/ppc: Support vector dup2 Aleksandar Markovic
` (4 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
For Altivec, this is always an expansion.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 2 +-
tcg/ppc/tcg-target.inc.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++-
tcg/ppc/tcg-target.opc.h | 8 ++++
3 files changed, 120 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 766706f..a130192 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -154,7 +154,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_shs_vec 0
#define TCG_TARGET_HAS_shv_vec 1
#define TCG_TARGET_HAS_cmp_vec 1
-#define TCG_TARGET_HAS_mul_vec 0
+#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 3eb18cb..3005c51 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -526,6 +526,25 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VSRAB VX4(772)
#define VSRAH VX4(836)
#define VSRAW VX4(900)
+#define VRLB VX4(4)
+#define VRLH VX4(68)
+#define VRLW VX4(132)
+
+#define VMULEUB VX4(520)
+#define VMULEUH VX4(584)
+#define VMULOUB VX4(8)
+#define VMULOUH VX4(72)
+#define VMSUMUHM VX4(38)
+
+#define VMRGHB VX4(12)
+#define VMRGHH VX4(76)
+#define VMRGHW VX4(140)
+#define VMRGLB VX4(268)
+#define VMRGLH VX4(332)
+#define VMRGLW VX4(396)
+
+#define VPKUHUM VX4(14)
+#define VPKUWUM VX4(78)
#define VAND VX4(1028)
#define VANDC VX4(1092)
@@ -2876,6 +2895,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_sarv_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
+ case INDEX_op_mul_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
@@ -2989,7 +3009,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
- sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 };
+ sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 },
+ mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
+ mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
+ muleu_op[4] = { VMULEUB, VMULEUH, 0, 0 },
+ mulou_op[4] = { VMULOUB, VMULOUH, 0, 0 },
+ pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
+ rotl_op[4] = { VRLB, VRLH, VRLW, 0 };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -3078,6 +3104,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_ppc_mrgh_vec:
+ insn = mrgh_op[vece];
+ break;
+ case INDEX_op_ppc_mrgl_vec:
+ insn = mrgl_op[vece];
+ break;
+ case INDEX_op_ppc_muleu_vec:
+ insn = muleu_op[vece];
+ break;
+ case INDEX_op_ppc_mulou_vec:
+ insn = mulou_op[vece];
+ break;
+ case INDEX_op_ppc_pkum_vec:
+ insn = pkum_op[vece];
+ break;
+ case INDEX_op_ppc_rotl_vec:
+ insn = rotl_op[vece];
+ break;
+ case INDEX_op_ppc_msum_vec:
+ tcg_debug_assert(vece == MO_16);
+ tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3]));
+ return;
+
case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */
case INDEX_op_dupi_vec: /* Always emitted via tcg_out_movi. */
case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */
@@ -3147,6 +3196,53 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
}
}
+static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
+ TCGv_vec v1, TCGv_vec v2)
+{
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+ TCGv_vec t3, t4;
+
+ switch (vece) {
+ case MO_8:
+ case MO_16:
+ vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0),
+ tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1),
+ tcgv_vec_arg(t1), tcgv_vec_arg(t2));
+ vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0),
+ tcgv_vec_arg(v0), tcgv_vec_arg(t1));
+ break;
+
+ case MO_32:
+ t3 = tcg_temp_new_vec(type);
+ t4 = tcg_temp_new_vec(type);
+ tcg_gen_dupi_vec(MO_8, t4, -16);
+ vec_gen_3(INDEX_op_ppc_rotl_vec, type, MO_32, tcgv_vec_arg(t1),
+ tcgv_vec_arg(v2), tcgv_vec_arg(t4));
+ vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2),
+ tcgv_vec_arg(v1), tcgv_vec_arg(v2));
+ tcg_gen_dupi_vec(MO_8, t3, 0);
+ vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t3),
+ tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(t3));
+ vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t3),
+ tcgv_vec_arg(t3), tcgv_vec_arg(t4));
+ tcg_gen_add_vec(MO_32, v0, t2, t3);
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t4);
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+}
+
void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
TCGArg a0, ...)
{
@@ -3173,6 +3269,10 @@ void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
v2 = temp_tcgv_vec(arg_temp(a2));
expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg));
break;
+ case INDEX_op_mul_vec:
+ v2 = temp_tcgv_vec(arg_temp(a2));
+ expand_vec_mul(type, vece, v0, v1, v2);
+ break;
default:
g_assert_not_reached();
}
@@ -3219,6 +3319,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
+ static const TCGTargetOpDef v_v_v_v
+ = { .args_ct_str = { "v", "v", "v", "v" } };
switch (op) {
case INDEX_op_goto_ptr:
@@ -3374,6 +3476,12 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_ppc_mrgh_vec:
+ case INDEX_op_ppc_mrgl_vec:
+ case INDEX_op_ppc_muleu_vec:
+ case INDEX_op_ppc_mulou_vec:
+ case INDEX_op_ppc_pkum_vec:
+ case INDEX_op_ppc_rotl_vec:
return &v_v_v;
case INDEX_op_not_vec:
case INDEX_op_dup_vec:
@@ -3382,6 +3490,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
return &v_r;
+ case INDEX_op_ppc_msum_vec:
+ return &v_v_v_v;
default:
return NULL;
diff --git a/tcg/ppc/tcg-target.opc.h b/tcg/ppc/tcg-target.opc.h
index 4816a6c..5c6a5ad 100644
--- a/tcg/ppc/tcg-target.opc.h
+++ b/tcg/ppc/tcg-target.opc.h
@@ -1,3 +1,11 @@
/* Target-specific opcodes for host vector expansion. These will be
emitted by tcg_expand_vec_op. For those familiar with GCC internals,
consider these to be UNSPEC with names. */
+
+DEF(ppc_mrgh_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_mrgl_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_msum_vec, 1, 3, 0, IMPLVEC)
+DEF(ppc_muleu_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_mulou_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_pkum_vec, 1, 2, 0, IMPLVEC)
+DEF(ppc_rotl_vec, 1, 2, 0, IMPLVEC)
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 13/16] tcg/ppc: Support vector dup2
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (11 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 12/16] tcg/ppc: Support vector multiply Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 14/16] tcg/ppc: Update vector support to v2.06 Aleksandar Markovic
` (3 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
This is only used for 32-bit hosts.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.inc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 3005c51..61732c1 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -3104,6 +3104,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_dup2_vec:
+ assert(TCG_TARGET_REG_BITS == 32);
+ /* With inputs a1 = xLxx, a2 = xHxx */
+ tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
+ tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
+ return;
+
case INDEX_op_ppc_mrgh_vec:
insn = mrgh_op[vece];
break;
@@ -3482,6 +3490,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ppc_mulou_vec:
case INDEX_op_ppc_pkum_vec:
case INDEX_op_ppc_rotl_vec:
+ case INDEX_op_dup2_vec:
return &v_v_v;
case INDEX_op_not_vec:
case INDEX_op_dup_vec:
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 14/16] tcg/ppc: Update vector support to v2.06
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (12 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 13/16] tcg/ppc: Support vector dup2 Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 15/16] tcg/ppc: Update vector support to v2.07 Aleksandar Markovic
` (2 subsequent siblings)
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
This includes double-word loads and stores, double-word load and splat,
double-word permute, and bit select. All of which require multiple
operations in the base Altivec instruction set.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 5 +++--
tcg/ppc/tcg-target.inc.c | 51 ++++++++++++++++++++++++++++++++++++++++++++----
2 files changed, 50 insertions(+), 6 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index a130192..40544f9 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -60,6 +60,7 @@ typedef enum {
extern bool have_isa_altivec;
extern bool have_isa_2_06;
+extern bool have_isa_2_06_vsx;
extern bool have_isa_3_00;
/* optional instructions automatically implemented */
@@ -141,7 +142,7 @@ extern bool have_isa_3_00;
* instruction and substituting two 32-bit stores makes the generated
* code quite large.
*/
-#define TCG_TARGET_HAS_v64 0
+#define TCG_TARGET_HAS_v64 have_isa_2_06_vsx
#define TCG_TARGET_HAS_v128 have_isa_altivec
#define TCG_TARGET_HAS_v256 0
@@ -157,7 +158,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec have_isa_2_06_vsx
#define TCG_TARGET_HAS_cmpsel_vec 0
void flush_icache_range(uintptr_t start, uintptr_t stop);
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 61732c1..0c2ad8d 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -66,6 +66,7 @@ static tcg_insn_unit *tb_ret_addr;
bool have_isa_altivec;
bool have_isa_2_06;
+bool have_isa_2_06_vsx;
bool have_isa_3_00;
#define HAVE_ISA_2_06 have_isa_2_06
@@ -470,9 +471,12 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define LVEBX XO31(7)
#define LVEHX XO31(39)
#define LVEWX XO31(71)
+#define LXSDX XO31(588) /* v2.06 */
+#define LXVDSX XO31(332) /* v2.06 */
#define STVX XO31(231)
#define STVEWX XO31(199)
+#define STXSDX XO31(716) /* v2.06 */
#define VADDSBS VX4(768)
#define VADDUBS VX4(512)
@@ -561,6 +565,9 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VSLDOI VX4(44)
+#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
+#define XXSEL (OPCD(60) | (3 << 4)) /* v2.06 */
+
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
@@ -887,11 +894,21 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
add = 0;
}
- load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
- if (TCG_TARGET_REG_BITS == 64) {
- new_pool_l2(s, rel, s->code_ptr, add, val, val);
+ if (have_isa_2_06_vsx) {
+ load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
+ load_insn |= VRT(ret) | RB(TCG_REG_TMP1) | 1;
+ if (TCG_TARGET_REG_BITS == 64) {
+ new_pool_label(s, val, rel, s->code_ptr, add);
+ } else {
+ new_pool_l2(s, rel, s->code_ptr, add, val, val);
+ }
} else {
- new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+ load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
+ if (TCG_TARGET_REG_BITS == 64) {
+ new_pool_l2(s, rel, s->code_ptr, add, val, val);
+ } else {
+ new_pool_l4(s, rel, s->code_ptr, add, val, val, val, val);
+ }
}
if (USE_REG_TB) {
@@ -1138,6 +1155,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
/* fallthru */
case TCG_TYPE_V64:
tcg_debug_assert(ret >= 32);
+ if (have_isa_2_06_vsx) {
+ tcg_out_mem_long(s, 0, LXSDX | 1, ret & 31, base, offset);
+ break;
+ }
assert((offset & 7) == 0);
tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset & -16);
if (offset & 8) {
@@ -1181,6 +1202,10 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
/* fallthru */
case TCG_TYPE_V64:
tcg_debug_assert(arg >= 32);
+ if (have_isa_2_06_vsx) {
+ tcg_out_mem_long(s, 0, STXSDX | 1, arg & 31, base, offset);
+ break;
+ }
assert((offset & 7) == 0);
if (offset & 8) {
tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8);
@@ -2900,6 +2925,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
return vece <= MO_32 ? -1 : 0;
+ case INDEX_op_bitsel_vec:
+ return have_isa_2_06_vsx;
default:
return 0;
}
@@ -2926,6 +2953,10 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16));
break;
case MO_64:
+ if (have_isa_2_06_vsx) {
+ tcg_out32(s, XXPERMDI | 7 | VRT(dst) | VRA(src) | VRB(src));
+ break;
+ }
tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8);
tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8);
break;
@@ -2970,6 +3001,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16));
break;
case MO_64:
+ if (have_isa_2_06_vsx) {
+ tcg_out_mem_long(s, 0, LXVDSX | 1, out, base, offset);
+ break;
+ }
assert((offset & 7) == 0);
tcg_out_mem_long(s, 0, LVX, out, base, offset & -16);
tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8);
@@ -3104,6 +3139,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_bitsel_vec:
+ tcg_out32(s, XXSEL | 0xf | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3]));
+ return;
+
case INDEX_op_dup2_vec:
assert(TCG_TARGET_REG_BITS == 32);
/* With inputs a1 = xLxx, a2 = xHxx */
@@ -3499,6 +3538,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
return &v_r;
+ case INDEX_op_bitsel_vec:
case INDEX_op_ppc_msum_vec:
return &v_v_v_v;
@@ -3517,6 +3557,9 @@ static void tcg_target_init(TCGContext *s)
}
if (hwcap & PPC_FEATURE_ARCH_2_06) {
have_isa_2_06 = true;
+ if (hwcap & PPC_FEATURE_HAS_VSX) {
+ have_isa_2_06_vsx = true;
+ }
}
#ifdef PPC_FEATURE2_ARCH_3_00
if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 15/16] tcg/ppc: Update vector support to v2.07
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (13 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 14/16] tcg/ppc: Update vector support to v2.06 Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 16/16] tcg/ppc: Update vector support to v3.00 Aleksandar Markovic
2019-06-23 17:36 ` [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes no-reply
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
This includes single-word loads and stores, lots of double-word
arithmetic, and a few extra logical operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 111 +++++++++++++++++++++++++++++++++++++----------
2 files changed, 91 insertions(+), 23 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 40544f9..b8355d0 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -61,6 +61,7 @@ typedef enum {
extern bool have_isa_altivec;
extern bool have_isa_2_06;
extern bool have_isa_2_06_vsx;
+extern bool have_isa_2_07_vsx;
extern bool have_isa_3_00;
/* optional instructions automatically implemented */
@@ -147,7 +148,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_v256 0
#define TCG_TARGET_HAS_andc_vec 1
-#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_orc_vec have_isa_2_07_vsx
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index 0c2ad8d..badbe2c 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -67,6 +67,7 @@ static tcg_insn_unit *tb_ret_addr;
bool have_isa_altivec;
bool have_isa_2_06;
bool have_isa_2_06_vsx;
+bool have_isa_2_07_vsx;
bool have_isa_3_00;
#define HAVE_ISA_2_06 have_isa_2_06
@@ -473,10 +474,12 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define LVEWX XO31(71)
#define LXSDX XO31(588) /* v2.06 */
#define LXVDSX XO31(332) /* v2.06 */
+#define LXSIWZX XO31(12) /* v2.07 */
#define STVX XO31(231)
#define STVEWX XO31(199)
#define STXSDX XO31(716) /* v2.06 */
+#define STXSIWX XO31(140) /* v2.07 */
#define VADDSBS VX4(768)
#define VADDUBS VX4(512)
@@ -487,6 +490,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VADDSWS VX4(896)
#define VADDUWS VX4(640)
#define VADDUWM VX4(128)
+#define VADDUDM VX4(192) /* v2.07 */
#define VSUBSBS VX4(1792)
#define VSUBUBS VX4(1536)
@@ -497,47 +501,62 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VSUBSWS VX4(1920)
#define VSUBUWS VX4(1664)
#define VSUBUWM VX4(1152)
+#define VSUBUDM VX4(1216) /* v2.07 */
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
+#define VMAXSD VX4(450) /* v2.07 */
#define VMAXUB VX4(2)
#define VMAXUH VX4(66)
#define VMAXUW VX4(130)
+#define VMAXUD VX4(194) /* v2.07 */
#define VMINSB VX4(770)
#define VMINSH VX4(834)
#define VMINSW VX4(898)
+#define VMINSD VX4(962) /* v2.07 */
#define VMINUB VX4(514)
#define VMINUH VX4(578)
#define VMINUW VX4(642)
+#define VMINUD VX4(706) /* v2.07 */
#define VCMPEQUB VX4(6)
#define VCMPEQUH VX4(70)
#define VCMPEQUW VX4(134)
+#define VCMPEQUD VX4(199) /* v2.07 */
#define VCMPGTSB VX4(774)
#define VCMPGTSH VX4(838)
#define VCMPGTSW VX4(902)
+#define VCMPGTSD VX4(967) /* v2.07 */
#define VCMPGTUB VX4(518)
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
+#define VCMPGTUD VX4(711) /* v2.07 */
#define VSLB VX4(260)
#define VSLH VX4(324)
#define VSLW VX4(388)
+#define VSLD VX4(1476) /* v2.07 */
#define VSRB VX4(516)
#define VSRH VX4(580)
#define VSRW VX4(644)
+#define VSRD VX4(1732) /* v2.07 */
#define VSRAB VX4(772)
#define VSRAH VX4(836)
#define VSRAW VX4(900)
+#define VSRAD VX4(964) /* v2.07 */
#define VRLB VX4(4)
#define VRLH VX4(68)
#define VRLW VX4(132)
+#define VRLD VX4(196) /* v2.07 */
#define VMULEUB VX4(520)
#define VMULEUH VX4(584)
+#define VMULEUW VX4(648) /* v2.07 */
#define VMULOUB VX4(8)
#define VMULOUH VX4(72)
+#define VMULOUW VX4(136) /* v2.07 */
+#define VMULUWM VX4(137) /* v2.07 */
#define VMSUMUHM VX4(38)
#define VMRGHB VX4(12)
@@ -555,6 +574,9 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VNOR VX4(1284)
#define VOR VX4(1156)
#define VXOR VX4(1220)
+#define VEQV VX4(1668) /* v2.07 */
+#define VNAND VX4(1412) /* v2.07 */
+#define VORC VX4(1348) /* v2.07 */
#define VSPLTB VX4(524)
#define VSPLTH VX4(588)
@@ -568,6 +590,11 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
#define XXSEL (OPCD(60) | (3 << 4)) /* v2.06 */
+#define MFVSRD XO31(51) /* v2.07 */
+#define MFVSRWZ XO31(115) /* v2.07 */
+#define MTVSRD XO31(179) /* v2.07 */
+#define MTVSRWZ XO31(179) /* v2.07 */
+
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
#define RA(r) ((r)<<16)
@@ -700,7 +727,15 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
if (ret < 32 && arg < 32) {
tcg_out32(s, OR | SAB(arg, ret, arg));
break;
- } else if (ret < 32 || arg < 32) {
+ } else if (ret < 32 && have_isa_2_07_vsx) {
+ tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD)
+ | VRT(arg) | RA(ret) | 1);
+ break;
+ } else if (arg < 32 && have_isa_2_07_vsx) {
+ tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD)
+ | VRT(ret) | RA(arg) | 1);
+ break;
+ } else {
/* Altivec does not support vector/integer moves. */
return false;
}
@@ -1140,6 +1175,10 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset);
break;
}
+ if (have_isa_2_07_vsx) {
+ tcg_out_mem_long(s, 0, LXSIWZX | 1, ret & 31, base, offset);
+ break;
+ }
assert((offset & 3) == 0);
tcg_out_mem_long(s, 0, LVEWX, ret & 31, base, offset);
shift = (offset - 4) & 0xc;
@@ -1186,6 +1225,10 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
tcg_out_mem_long(s, STW, STWX, arg, base, offset);
break;
}
+ if (have_isa_2_07_vsx) {
+ tcg_out_mem_long(s, 0, STXSIWX | 1, arg & 31, base, offset);
+ break;
+ }
assert((offset & 3) == 0);
shift = (offset - 4) & 0xc;
if (shift) {
@@ -2905,26 +2948,37 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
return 1;
+ case INDEX_op_orc_vec:
+ return have_isa_2_07_vsx;
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
case INDEX_op_smax_vec:
case INDEX_op_smin_vec:
case INDEX_op_umax_vec:
case INDEX_op_umin_vec:
+ case INDEX_op_shlv_vec:
+ case INDEX_op_shrv_vec:
+ case INDEX_op_sarv_vec:
+ return vece <= MO_32 || have_isa_2_07_vsx;
case INDEX_op_ssadd_vec:
case INDEX_op_sssub_vec:
case INDEX_op_usadd_vec:
case INDEX_op_ussub_vec:
- case INDEX_op_shlv_vec:
- case INDEX_op_shrv_vec:
- case INDEX_op_sarv_vec:
return vece <= MO_32;
case INDEX_op_cmp_vec:
- case INDEX_op_mul_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
- return vece <= MO_32 ? -1 : 0;
+ return vece <= MO_32 || have_isa_2_07_vsx ? -1 : 0;
+ case INDEX_op_mul_vec:
+ switch (vece) {
+ case MO_8:
+ case MO_16:
+ return -1;
+ case MO_32:
+ return have_isa_2_07_vsx ? 1 : -1;
+ }
+ return 0;
case INDEX_op_bitsel_vec:
return have_isa_2_06_vsx;
default:
@@ -3029,28 +3083,28 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
static const uint32_t
- add_op[4] = { VADDUBM, VADDUHM, VADDUWM, 0 },
- sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, 0 },
- eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, 0 },
- gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, 0 },
- gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, 0 },
+ add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
+ sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
+ eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
+ gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
+ gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 },
sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 },
ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 },
- umin_op[4] = { VMINUB, VMINUH, VMINUW, 0 },
- smin_op[4] = { VMINSB, VMINSH, VMINSW, 0 },
- umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, 0 },
- smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, 0 },
- shlv_op[4] = { VSLB, VSLH, VSLW, 0 },
- shrv_op[4] = { VSRB, VSRH, VSRW, 0 },
- sarv_op[4] = { VSRAB, VSRAH, VSRAW, 0 },
+ umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD },
+ smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD },
+ umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD },
+ smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD },
+ shlv_op[4] = { VSLB, VSLH, VSLW, VSLD },
+ shrv_op[4] = { VSRB, VSRH, VSRW, VSRD },
+ sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD },
mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 },
mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 },
- muleu_op[4] = { VMULEUB, VMULEUH, 0, 0 },
- mulou_op[4] = { VMULOUB, VMULOUH, 0, 0 },
+ muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 },
+ mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 },
pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 },
- rotl_op[4] = { VRLB, VRLH, VRLW, 0 };
+ rotl_op[4] = { VRLB, VRLH, VRLW, VRLD };
TCGType type = vecl + TCG_TYPE_V64;
TCGArg a0 = args[0], a1 = args[1], a2 = args[2];
@@ -3073,6 +3127,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sub_vec:
insn = sub_op[vece];
break;
+ case INDEX_op_mul_vec:
+ tcg_debug_assert(vece == MO_32 && have_isa_2_07_vsx);
+ insn = VMULUWM;
+ break;
case INDEX_op_ssadd_vec:
insn = ssadd_op[vece];
break;
@@ -3122,6 +3180,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
insn = VNOR;
a2 = a1;
break;
+ case INDEX_op_orc_vec:
+ insn = VORC;
+ break;
case INDEX_op_cmp_vec:
switch (args[3]) {
@@ -3202,7 +3263,7 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
{
bool need_swap = false, need_inv = false;
- tcg_debug_assert(vece <= MO_32);
+ tcg_debug_assert(vece <= MO_32 || have_isa_2_07_vsx);
switch (cond) {
case TCG_COND_EQ:
@@ -3266,6 +3327,7 @@ static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0,
break;
case MO_32:
+ tcg_debug_assert(!have_isa_2_07_vsx);
t3 = tcg_temp_new_vec(type);
t4 = tcg_temp_new_vec(type);
tcg_gen_dupi_vec(MO_8, t4, -16);
@@ -3561,6 +3623,11 @@ static void tcg_target_init(TCGContext *s)
have_isa_2_06_vsx = true;
}
}
+ if (hwcap2 & PPC_FEATURE2_ARCH_2_07) {
+ if (hwcap & PPC_FEATURE_HAS_VSX) {
+ have_isa_2_07_vsx = true;
+ }
+ }
#ifdef PPC_FEATURE2_ARCH_3_00
if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
have_isa_3_00 = true;
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Qemu-devel] [PATCH v5 16/16] tcg/ppc: Update vector support to v3.00
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (14 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 15/16] tcg/ppc: Update vector support to v2.07 Aleksandar Markovic
@ 2019-06-23 17:04 ` Aleksandar Markovic
2019-06-23 17:36 ` [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes no-reply
16 siblings, 0 replies; 18+ messages in thread
From: Aleksandar Markovic @ 2019-06-23 17:04 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, David Gibson --cc=amarkovic @ wavecomp . com,
Mark Cave-Ayland, Aleksandar Markovic, hsp.cat7
From: Richard Henderson <richard.henderson@linaro.org>
This includes vector load/store with immediate offset, some extra
move and splat insns, compare ne, and negate.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
tcg/ppc/tcg-target.h | 3 +-
tcg/ppc/tcg-target.inc.c | 103 ++++++++++++++++++++++++++++++++++++++++++-----
2 files changed, 94 insertions(+), 12 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index b8355d0..533f0ef 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -63,6 +63,7 @@ extern bool have_isa_2_06;
extern bool have_isa_2_06_vsx;
extern bool have_isa_2_07_vsx;
extern bool have_isa_3_00;
+extern bool have_isa_3_00_vsx;
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
@@ -150,7 +151,7 @@ extern bool have_isa_3_00;
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec have_isa_2_07_vsx
#define TCG_TARGET_HAS_not_vec 1
-#define TCG_TARGET_HAS_neg_vec 0
+#define TCG_TARGET_HAS_neg_vec have_isa_3_00_vsx
#define TCG_TARGET_HAS_abs_vec 0
#define TCG_TARGET_HAS_shi_vec 0
#define TCG_TARGET_HAS_shs_vec 0
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index badbe2c..6cc56cf 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -69,6 +69,7 @@ bool have_isa_2_06;
bool have_isa_2_06_vsx;
bool have_isa_2_07_vsx;
bool have_isa_3_00;
+bool have_isa_3_00_vsx;
#define HAVE_ISA_2_06 have_isa_2_06
#define HAVE_ISEL have_isa_2_06
@@ -475,11 +476,16 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define LXSDX XO31(588) /* v2.06 */
#define LXVDSX XO31(332) /* v2.06 */
#define LXSIWZX XO31(12) /* v2.07 */
+#define LXV (OPCD(61) | 1) /* v3.00 */
+#define LXSD (OPCD(57) | 2) /* v3.00 */
+#define LXVWSX XO31(364) /* v3.00 */
#define STVX XO31(231)
#define STVEWX XO31(199)
#define STXSDX XO31(716) /* v2.06 */
#define STXSIWX XO31(140) /* v2.07 */
+#define STXV (OPCD(61) | 5) /* v3.00 */
+#define STXSD (OPCD(61) | 2) /* v3.00 */
#define VADDSBS VX4(768)
#define VADDUBS VX4(512)
@@ -503,6 +509,9 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VSUBUWM VX4(1152)
#define VSUBUDM VX4(1216) /* v2.07 */
+#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */
+#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */
+
#define VMAXSB VX4(258)
#define VMAXSH VX4(322)
#define VMAXSW VX4(386)
@@ -532,6 +541,9 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VCMPGTUH VX4(582)
#define VCMPGTUW VX4(646)
#define VCMPGTUD VX4(711) /* v2.07 */
+#define VCMPNEB VX4(7) /* v3.00 */
+#define VCMPNEH VX4(71) /* v3.00 */
+#define VCMPNEW VX4(135) /* v3.00 */
#define VSLB VX4(260)
#define VSLH VX4(324)
@@ -589,11 +601,14 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define XXPERMDI (OPCD(60) | (10 << 3)) /* v2.06 */
#define XXSEL (OPCD(60) | (3 << 4)) /* v2.06 */
+#define XXSPLTIB (OPCD(60) | (360 << 1)) /* v3.00 */
#define MFVSRD XO31(51) /* v2.07 */
#define MFVSRWZ XO31(115) /* v2.07 */
#define MTVSRD XO31(179) /* v2.07 */
#define MTVSRWZ XO31(179) /* v2.07 */
+#define MTVSRDD XO31(435) /* v3.00 */
+#define MTVSRWS XO31(403) /* v3.00 */
#define RT(r) ((r)<<21)
#define RS(r) ((r)<<21)
@@ -917,6 +932,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, TCGReg ret,
return;
}
}
+ if (have_isa_3_00_vsx && val == (tcg_target_long)dup_const(MO_8, val)) {
+ tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11) | 1);
+ return;
+ }
/*
* Otherwise we must load the value from the constant pool.
@@ -1105,7 +1124,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
TCGReg base, tcg_target_long offset)
{
tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
- bool is_store = false;
+ bool is_int_store = false;
TCGReg rs = TCG_REG_TMP1;
switch (opi) {
@@ -1118,11 +1137,20 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
break;
}
break;
+ case LXSD:
+ case STXSD:
+ align = 3;
+ break;
+ case LXV: case LXV | 8:
+ case STXV: case STXV | 8:
+ /* The |8 cases force altivec registers. */
+ align = 15;
+ break;
case STD:
align = 3;
/* FALLTHRU */
case STB: case STH: case STW:
- is_store = true;
+ is_int_store = true;
break;
}
@@ -1131,7 +1159,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
if (rs == base) {
rs = TCG_REG_R0;
}
- tcg_debug_assert(!is_store || rs != rt);
+ tcg_debug_assert(!is_int_store || rs != rt);
tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
tcg_out32(s, opx | TAB(rt, base, rs));
return;
@@ -1195,7 +1223,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
case TCG_TYPE_V64:
tcg_debug_assert(ret >= 32);
if (have_isa_2_06_vsx) {
- tcg_out_mem_long(s, 0, LXSDX | 1, ret & 31, base, offset);
+ tcg_out_mem_long(s, have_isa_3_00_vsx ? LXSD : 0, LXSDX | 1,
+ ret & 31, base, offset);
break;
}
assert((offset & 7) == 0);
@@ -1207,7 +1236,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
case TCG_TYPE_V128:
tcg_debug_assert(ret >= 32);
assert((offset & 15) == 0);
- tcg_out_mem_long(s, 0, LVX, ret & 31, base, offset);
+ tcg_out_mem_long(s, have_isa_3_00_vsx ? LXV | 8 : 0, LVX,
+ ret & 31, base, offset);
break;
default:
g_assert_not_reached();
@@ -1246,7 +1276,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
case TCG_TYPE_V64:
tcg_debug_assert(arg >= 32);
if (have_isa_2_06_vsx) {
- tcg_out_mem_long(s, 0, STXSDX | 1, arg & 31, base, offset);
+ tcg_out_mem_long(s, have_isa_3_00_vsx ? STXSD : 0,
+ STXSDX | 1, arg & 31, base, offset);
break;
}
assert((offset & 7) == 0);
@@ -1259,7 +1290,8 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
break;
case TCG_TYPE_V128:
tcg_debug_assert(arg >= 32);
- tcg_out_mem_long(s, 0, STVX, arg & 31, base, offset);
+ tcg_out_mem_long(s, have_isa_3_00_vsx ? STXV | 8 : 0, STVX,
+ arg & 31, base, offset);
break;
default:
g_assert_not_reached();
@@ -2970,6 +3002,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
return vece <= MO_32 || have_isa_2_07_vsx ? -1 : 0;
+ case INDEX_op_neg_vec:
+ return vece >= MO_32 && have_isa_3_00_vsx;
case INDEX_op_mul_vec:
switch (vece) {
case MO_8:
@@ -2990,7 +3024,22 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
TCGReg dst, TCGReg src)
{
tcg_debug_assert(dst >= 32);
- tcg_debug_assert(src >= 32);
+
+ /* Splat from integer reg allowed via constraints for v3.00. */
+ if (src < 32) {
+ tcg_debug_assert(have_isa_3_00_vsx);
+ switch (vece) {
+ case MO_64:
+ tcg_out32(s, MTVSRDD | 1 | VRT(dst) | RA(src) | RB(src));
+ return true;
+ case MO_32:
+ tcg_out32(s, MTVSRWS | 1 | VRT(dst) | RA(src));
+ return true;
+ default:
+ /* Fail, so that we fall back on either dupm or mov+dup. */
+ return false;
+ }
+ }
/*
* Recall we use (or emulate) VSX integer loads, so the integer is
@@ -3029,7 +3078,11 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
out &= 31;
switch (vece) {
case MO_8:
- tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
+ if (have_isa_3_00_vsx) {
+ tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
+ } else {
+ tcg_out_mem_long(s, 0, LVEBX, out, base, offset);
+ }
elt = extract32(offset, 0, 4);
#ifndef HOST_WORDS_BIGENDIAN
elt ^= 15;
@@ -3038,7 +3091,11 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
break;
case MO_16:
assert((offset & 1) == 0);
- tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
+ if (have_isa_3_00_vsx) {
+ tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16);
+ } else {
+ tcg_out_mem_long(s, 0, LVEHX, out, base, offset);
+ }
elt = extract32(offset, 1, 3);
#ifndef HOST_WORDS_BIGENDIAN
elt ^= 7;
@@ -3046,6 +3103,10 @@ static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16));
break;
case MO_32:
+ if (have_isa_3_00_vsx) {
+ tcg_out_mem_long(s, 0, LXVWSX | 1, out, base, offset);
+ break;
+ }
assert((offset & 3) == 0);
tcg_out_mem_long(s, 0, LVEWX, out, base, offset);
elt = extract32(offset, 2, 2);
@@ -3085,7 +3146,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const uint32_t
add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
+ neg_op[4] = { 0, 0, VNEGW, VNEGD },
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
+ ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD },
gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD },
ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 },
@@ -3127,6 +3190,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sub_vec:
insn = sub_op[vece];
break;
+ case INDEX_op_neg_vec:
+ insn = neg_op[vece];
+ a2 = a1;
+ a1 = 0;
+ break;
case INDEX_op_mul_vec:
tcg_debug_assert(vece == MO_32 && have_isa_2_07_vsx);
insn = VMULUWM;
@@ -3189,6 +3257,9 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case TCG_COND_EQ:
insn = eq_op[vece];
break;
+ case TCG_COND_NE:
+ insn = ne_op[vece];
+ break;
case TCG_COND_GT:
insn = gts_op[vece];
break;
@@ -3271,6 +3342,10 @@ static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0,
case TCG_COND_GTU:
break;
case TCG_COND_NE:
+ if (have_isa_3_00_vsx && vece <= MO_32) {
+ break;
+ }
+ /* fall through */
case TCG_COND_LE:
case TCG_COND_LEU:
need_inv = true;
@@ -3426,6 +3501,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
static const TCGTargetOpDef sub2
= { .args_ct_str = { "r", "r", "rI", "rZM", "r", "r" } };
static const TCGTargetOpDef v_r = { .args_ct_str = { "v", "r" } };
+ static const TCGTargetOpDef v_vr = { .args_ct_str = { "v", "vr" } };
static const TCGTargetOpDef v_v = { .args_ct_str = { "v", "v" } };
static const TCGTargetOpDef v_v_v = { .args_ct_str = { "v", "v", "v" } };
static const TCGTargetOpDef v_v_v_v
@@ -3594,8 +3670,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_dup2_vec:
return &v_v_v;
case INDEX_op_not_vec:
- case INDEX_op_dup_vec:
+ case INDEX_op_neg_vec:
return &v_v;
+ case INDEX_op_dup_vec:
+ return have_isa_3_00_vsx ? &v_vr : &v_v;
case INDEX_op_ld_vec:
case INDEX_op_st_vec:
case INDEX_op_dupm_vec:
@@ -3631,6 +3709,9 @@ static void tcg_target_init(TCGContext *s)
#ifdef PPC_FEATURE2_ARCH_3_00
if (hwcap2 & PPC_FEATURE2_ARCH_3_00) {
have_isa_3_00 = true;
+ if (hwcap & PPC_FEATURE_HAS_VSX) {
+ have_isa_3_00_vsx = true;
+ }
}
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes
2019-06-23 17:04 [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes Aleksandar Markovic
` (15 preceding siblings ...)
2019-06-23 17:04 ` [Qemu-devel] [PATCH v5 16/16] tcg/ppc: Update vector support to v3.00 Aleksandar Markovic
@ 2019-06-23 17:36 ` no-reply
16 siblings, 0 replies; 18+ messages in thread
From: no-reply @ 2019-06-23 17:36 UTC (permalink / raw)
To: aleksandar.markovic
Cc: richard.henderson, mark.cave-ayland, qemu-devel, amarkovic,
hsp.cat7, david
Patchew URL: https://patchew.org/QEMU/1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [Qemu-devel] [PATCH v5 00/16] tcg/ppc: Add vector opcodes
Type: series
Message-id: 1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
From https://github.com/patchew-project/qemu
* [new tag] patchew/1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com -> patchew/1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com
Switched to a new branch 'test'
22d133b7d3 tcg/ppc: Update vector support to v3.00
90bbf51163 tcg/ppc: Update vector support to v2.07
b5335688c8 tcg/ppc: Update vector support to v2.06
b521901488 tcg/ppc: Support vector dup2
8924e68f97 tcg/ppc: Support vector multiply
e293fff80b tcg/ppc: Support vector shift by immediate
f690223722 tcg/ppc: Add empty file tcg-target.opc.h
e4e6419f8c tcg/ppc: Prepare case for vector multiply
7957f8f41c tcg/ppc: Add support for vector saturated add/subtract
fe805396ae tcg/ppc: Add support for vector add/subtract
5cb6cd0fc0 tcg/ppc: Add support for vector maximum/minimum
4747cecdb1 tcg/ppc: Add support for load/store/logic/comparison
421bc6d7d3 tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC()
0379705f8d tcg/ppc: Introduce macro VX4()
7fc4554647 tcg/ppc: Introduce flag have_isa_altivec
29c55ddd9f tcg/ppc: Introduce Altivec registers
=== OUTPUT BEGIN ===
1/16 Checking commit 29c55ddd9f2e (tcg/ppc: Introduce Altivec registers)
2/16 Checking commit 7fc455464789 (tcg/ppc: Introduce flag have_isa_altivec)
3/16 Checking commit 0379705f8d31 (tcg/ppc: Introduce macro VX4())
ERROR: spaces required around that '|' (ctx:VxV)
#21: FILE: tcg/ppc/tcg-target.inc.c:323:
+#define VX4(opc) (OPCD(4)|(opc))
^
total: 1 errors, 0 warnings, 7 lines checked
Patch 3/16 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/16 Checking commit 421bc6d7d308 (tcg/ppc: Introduce macros VRT(), VRA(), VRB(), VRC())
5/16 Checking commit 4747cecdb1b0 (tcg/ppc: Add support for load/store/logic/comparison)
6/16 Checking commit 5cb6cd0fc043 (tcg/ppc: Add support for vector maximum/minimum)
7/16 Checking commit fe805396aee3 (tcg/ppc: Add support for vector add/subtract)
8/16 Checking commit 7957f8f41c63 (tcg/ppc: Add support for vector saturated add/subtract)
9/16 Checking commit e4e6419f8c88 (tcg/ppc: Prepare case for vector multiply)
10/16 Checking commit f69022372202 (tcg/ppc: Add empty file tcg-target.opc.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#14:
new file mode 100644
WARNING: Block comments use a leading /* on a separate line
#19: FILE: tcg/ppc/tcg-target.opc.h:1:
+/* Target-specific opcodes for host vector expansion. These will be
WARNING: Block comments use * on subsequent lines
#20: FILE: tcg/ppc/tcg-target.opc.h:2:
+/* Target-specific opcodes for host vector expansion. These will be
+ emitted by tcg_expand_vec_op. For those familiar with GCC internals,
WARNING: Block comments use a trailing */ on a separate line
#21: FILE: tcg/ppc/tcg-target.opc.h:3:
+ consider these to be UNSPEC with names. */
total: 0 errors, 4 warnings, 3 lines checked
Patch 10/16 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/16 Checking commit e293fff80b39 (tcg/ppc: Support vector shift by immediate)
12/16 Checking commit 8924e68f97c6 (tcg/ppc: Support vector multiply)
ERROR: code indent should never use tabs
#133: FILE: tcg/ppc/tcg-target.inc.c:3219:
+^Ibreak;$
total: 1 errors, 0 warnings, 185 lines checked
Patch 12/16 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/16 Checking commit b52190148845 (tcg/ppc: Support vector dup2)
14/16 Checking commit b5335688c827 (tcg/ppc: Update vector support to v2.06)
15/16 Checking commit 90bbf5116349 (tcg/ppc: Update vector support to v2.07)
16/16 Checking commit 22d133b7d326 (tcg/ppc: Update vector support to v3.00)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1561309489-16146-1-git-send-email-aleksandar.markovic@rt-rk.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 18+ messages in thread