* [Qemu-devel] [PATCH v2 0/2] configure: Define target access alignment in configure @ 2019-07-22 3:19 tony.nguyen 2019-07-22 3:27 ` [Qemu-devel] [PATCH v2 1/2] " tony.nguyen 2019-07-22 3:28 ` [Qemu-devel] [PATCH v2 2/2] configure: Cosmetic yes to "yes" for consistency tony.nguyen 0 siblings, 2 replies; 6+ messages in thread From: tony.nguyen @ 2019-07-22 3:19 UTC (permalink / raw) To: qemu-devel Cc: ehabkost, arikalo, mark.cave-ayland, jcmvbkbc, atar4qemu, amarkovic, aurelien, rth Move the define of target access alignment earlier from target/foo/cpu.h to configure. Suggested in Richard Henderson's reply to "[PATCH 1/4] tcg: TCGMemOp is now accelerator independent MemOp" Analysed target/foo/cpu.h for more candidates to define earlier but did not spot any other straight forward predicates. Possible future clean ups: - TCG_GUEST_DEFAULT_MO and TCG_TARGET_DEFAULT_MO seems like duplicates - TARGET_INSN_START_EXTRA_WORDS 1 seems redundant as ifndef value is 1 v2: - split cosmetic changes into separate patch - cc corresponding maintainers Thanks to Aleksandar Markovic for the guide in v1 =) Tony Nguyen (2): configure: Define TARGET_ALIGNED_ONLY earlier configure: Cosmetic yes to "yes" for consistency configure | 12 ++++++++++-- include/exec/poison.h | 1 + include/qom/cpu.h | 2 +- target/alpha/cpu.h | 2 -- target/hppa/cpu.h | 1 - target/mips/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- tcg/tcg.c | 2 +- tcg/tcg.h | 8 +++++--- 11 files changed, 18 insertions(+), 18 deletions(-) -- 1.8.3.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v2 1/2] configure: Define target access alignment in configure 2019-07-22 3:19 [Qemu-devel] [PATCH v2 0/2] configure: Define target access alignment in configure tony.nguyen @ 2019-07-22 3:27 ` tony.nguyen 2019-07-22 10:54 ` Philippe Mathieu-Daudé 2019-07-23 16:18 ` Aleksandar Markovic 2019-07-22 3:28 ` [Qemu-devel] [PATCH v2 2/2] configure: Cosmetic yes to "yes" for consistency tony.nguyen 1 sibling, 2 replies; 6+ messages in thread From: tony.nguyen @ 2019-07-22 3:27 UTC (permalink / raw) To: qemu-devel Cc: ehabkost, arikalo, mark.cave-ayland, jcmvbkbc, aurelien, amarkovic, atar4qemu, rth Move the define of target access alignment earlier from target/foo/cpu.h to configure. Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> --- configure | 10 +++++++++- include/exec/poison.h | 1 + include/qom/cpu.h | 2 +- target/alpha/cpu.h | 2 -- target/hppa/cpu.h | 1 - target/mips/cpu.h | 2 -- target/sh4/cpu.h | 2 -- target/sparc/cpu.h | 2 -- target/xtensa/cpu.h | 2 -- tcg/tcg.c | 2 +- tcg/tcg.h | 8 +++++--- 11 files changed, 17 insertions(+), 17 deletions(-) diff --git a/configure b/configure index eb635c3..8316a16 100755 --- a/configure +++ b/configure @@ -7424,8 +7424,13 @@ for target in $target_list; do target_dir="$target" config_target_mak=$target_dir/config-target.mak target_name=$(echo $target | cut -d '-' -f 1) +target_aligned_only="no" +case "$target_name" in + alpha|hppa|mips64el|mips64|mipsel|mips|mipsn32|mipsn32el|sh4|sh4eb|sparc|sparc64|sparc32plus|xtensa|xtensaeb) + target_aligned_only="yes" + ;; +esac target_bigendian="no" - case "$target_name" in armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb) target_bigendian=yes @@ -7710,6 +7715,9 @@ fi if supported_whpx_target $target; then echo "CONFIG_WHPX=y" >> $config_target_mak fi +if test "$target_aligned_only" = "yes" ; then + echo "TARGET_ALIGNED_ONLY=y" >> $config_target_mak +fi if test "$target_bigendian" = "yes" ; then echo "TARGET_WORDS_BIGENDIAN=y" >> $config_target_mak fi diff --git a/include/exec/poison.h b/include/exec/poison.h index b862320..955eb86 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -35,6 +35,7 @@ #pragma GCC poison TARGET_UNICORE32 #pragma GCC poison TARGET_XTENSA +#pragma GCC poison TARGET_ALIGNED_ONLY #pragma GCC poison TARGET_HAS_BFLT #pragma GCC poison TARGET_NAME #pragma GCC poison TARGET_SUPPORTS_MTTCG diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 5ee0046..9b50b73 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -89,7 +89,7 @@ struct TranslationBlock; * @do_unassigned_access: Callback for unassigned access handling. * (this is deprecated: new targets should use do_transaction_failed instead) * @do_unaligned_access: Callback for unaligned access handling, if - * the target defines #ALIGNED_ONLY. + * the target defines #TARGET_ALIGNED_ONLY. * @do_transaction_failed: Callback for handling failed memory transactions * (ie bus faults or external aborts; not MMU faults) * @virtio_is_big_endian: Callback to return %true if a CPU which supports diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index b3e8a82..16eb804 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -23,8 +23,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define ALIGNED_ONLY - /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index aab251b..2be67c2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -30,7 +30,6 @@ basis. It's probably easier to fall back to a strong memory model. */ #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL -#define ALIGNED_ONLY #define MMU_KERNEL_IDX 0 #define MMU_USER_IDX 3 #define MMU_PHYS_IDX 4 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 21c0615..c13cd4e 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1,8 +1,6 @@ #ifndef MIPS_CPU_H #define MIPS_CPU_H -#define ALIGNED_ONLY - #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index aee733e..ecaa7a1 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -23,8 +23,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define ALIGNED_ONLY - /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) #define SH_CPU_SH7750S (1 << 1) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 8ed2250..1406f0b 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -5,8 +5,6 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" -#define ALIGNED_ONLY - #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 #else diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 2c27713..0459243 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -32,8 +32,6 @@ #include "exec/cpu-defs.h" #include "xtensa-isa.h" -#define ALIGNED_ONLY - /* Xtensa processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/tcg/tcg.c b/tcg/tcg.c index be2c33c..8d23fb0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1926,7 +1926,7 @@ static const char * const ldst_name[] = }; static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { -#ifdef ALIGNED_ONLY +#ifdef TARGET_ALIGNED_ONLY [MO_UNALN >> MO_ASHIFT] = "un+", [MO_ALIGN >> MO_ASHIFT] = "", #else diff --git a/tcg/tcg.h b/tcg/tcg.h index b411e17..529acb2 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -333,10 +333,12 @@ typedef enum TCGMemOp { MO_TE = MO_LE, #endif - /* MO_UNALN accesses are never checked for alignment. + /* + * MO_UNALN accesses are never checked for alignment. * MO_ALIGN accesses will result in a call to the CPU's * do_unaligned_access hook if the guest address is not aligned. - * The default depends on whether the target CPU defines ALIGNED_ONLY. + * The default depends on whether the target CPU defines + * TARGET_ALIGNED_ONLY. * * Some architectures (e.g. ARMv8) need the address which is aligned * to a size more than the size of the memory access. @@ -353,7 +355,7 @@ typedef enum TCGMemOp { */ MO_ASHIFT = 4, MO_AMASK = 7 << MO_ASHIFT, -#ifdef ALIGNED_ONLY +#ifdef TARGET_ALIGNED_ONLY MO_ALIGN = 0, MO_UNALN = MO_AMASK, #else -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/2] configure: Define target access alignment in configure 2019-07-22 3:27 ` [Qemu-devel] [PATCH v2 1/2] " tony.nguyen @ 2019-07-22 10:54 ` Philippe Mathieu-Daudé 2019-07-23 16:18 ` Aleksandar Markovic 1 sibling, 0 replies; 6+ messages in thread From: Philippe Mathieu-Daudé @ 2019-07-22 10:54 UTC (permalink / raw) To: tony.nguyen, qemu-devel Cc: ehabkost, arikalo, mark.cave-ayland, jcmvbkbc, atar4qemu, amarkovic, aurelien, rth Hi Tony, On 7/22/19 5:27 AM, tony.nguyen@bt.com wrote: > Move the define of target access alignment earlier from > target/foo/cpu.h to configure. > You missed: Suggested-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> The single change from your v1 is: - target_bigendian=yes + target_bigendian="yes" So you can keep the tag from the reviewers who already checked your patch, so they don't have to look at it again: Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Anyway this patch is already queued by Paolo. Regards, Phil. > --- > configure | 10 +++++++++- > include/exec/poison.h | 1 + > include/qom/cpu.h | 2 +- > target/alpha/cpu.h | 2 -- > target/hppa/cpu.h | 1 - > target/mips/cpu.h | 2 -- > target/sh4/cpu.h | 2 -- > target/sparc/cpu.h | 2 -- > target/xtensa/cpu.h | 2 -- > tcg/tcg.c | 2 +- > tcg/tcg.h | 8 +++++--- > 11 files changed, 17 insertions(+), 17 deletions(-) > > diff --git a/configure b/configure > index eb635c3..8316a16 100755 > --- a/configure > +++ b/configure > @@ -7424,8 +7424,13 @@ for target in $target_list; do > target_dir="$target" > config_target_mak=$target_dir/config-target.mak > target_name=$(echo $target | cut -d '-' -f 1) > +target_aligned_only="no" > +case "$target_name" in > + alpha|hppa|mips64el|mips64|mipsel|mips|mipsn32|mipsn32el|sh4|sh4eb|sparc|sparc64|sparc32plus|xtensa|xtensaeb) > + target_aligned_only="yes" > + ;; > +esac > target_bigendian="no" > - > case "$target_name" in > armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb) > target_bigendian=yes > @@ -7710,6 +7715,9 @@ fi > if supported_whpx_target $target; then > echo "CONFIG_WHPX=y" >> $config_target_mak > fi > +if test "$target_aligned_only" = "yes" ; then > + echo "TARGET_ALIGNED_ONLY=y" >> $config_target_mak > +fi > if test "$target_bigendian" = "yes" ; then > echo "TARGET_WORDS_BIGENDIAN=y" >> $config_target_mak > fi > diff --git a/include/exec/poison.h b/include/exec/poison.h > index b862320..955eb86 100644 > --- a/include/exec/poison.h > +++ b/include/exec/poison.h > @@ -35,6 +35,7 @@ > #pragma GCC poison TARGET_UNICORE32 > #pragma GCC poison TARGET_XTENSA > > +#pragma GCC poison TARGET_ALIGNED_ONLY > #pragma GCC poison TARGET_HAS_BFLT > #pragma GCC poison TARGET_NAME > #pragma GCC poison TARGET_SUPPORTS_MTTCG > diff --git a/include/qom/cpu.h b/include/qom/cpu.h > index 5ee0046..9b50b73 100644 > --- a/include/qom/cpu.h > +++ b/include/qom/cpu.h > @@ -89,7 +89,7 @@ struct TranslationBlock; > * @do_unassigned_access: Callback for unassigned access handling. > * (this is deprecated: new targets should use do_transaction_failed instead) > * @do_unaligned_access: Callback for unaligned access handling, if > - * the target defines #ALIGNED_ONLY. > + * the target defines #TARGET_ALIGNED_ONLY. > * @do_transaction_failed: Callback for handling failed memory transactions > * (ie bus faults or external aborts; not MMU faults) > * @virtio_is_big_endian: Callback to return %true if a CPU which supports > diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h > index b3e8a82..16eb804 100644 > --- a/target/alpha/cpu.h > +++ b/target/alpha/cpu.h > @@ -23,8 +23,6 @@ > #include "cpu-qom.h" > #include "exec/cpu-defs.h" > > -#define ALIGNED_ONLY > - > /* Alpha processors have a weak memory model */ > #define TCG_GUEST_DEFAULT_MO (0) > > diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h > index aab251b..2be67c2 100644 > --- a/target/hppa/cpu.h > +++ b/target/hppa/cpu.h > @@ -30,7 +30,6 @@ > basis. It's probably easier to fall back to a strong memory model. */ > #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL > > -#define ALIGNED_ONLY > #define MMU_KERNEL_IDX 0 > #define MMU_USER_IDX 3 > #define MMU_PHYS_IDX 4 > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > index 21c0615..c13cd4e 100644 > --- a/target/mips/cpu.h > +++ b/target/mips/cpu.h > @@ -1,8 +1,6 @@ > #ifndef MIPS_CPU_H > #define MIPS_CPU_H > > -#define ALIGNED_ONLY > - > #include "cpu-qom.h" > #include "exec/cpu-defs.h" > #include "fpu/softfloat.h" > diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h > index aee733e..ecaa7a1 100644 > --- a/target/sh4/cpu.h > +++ b/target/sh4/cpu.h > @@ -23,8 +23,6 @@ > #include "cpu-qom.h" > #include "exec/cpu-defs.h" > > -#define ALIGNED_ONLY > - > /* CPU Subtypes */ > #define SH_CPU_SH7750 (1 << 0) > #define SH_CPU_SH7750S (1 << 1) > diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h > index 8ed2250..1406f0b 100644 > --- a/target/sparc/cpu.h > +++ b/target/sparc/cpu.h > @@ -5,8 +5,6 @@ > #include "cpu-qom.h" > #include "exec/cpu-defs.h" > > -#define ALIGNED_ONLY > - > #if !defined(TARGET_SPARC64) > #define TARGET_DPREGS 16 > #else > diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h > index 2c27713..0459243 100644 > --- a/target/xtensa/cpu.h > +++ b/target/xtensa/cpu.h > @@ -32,8 +32,6 @@ > #include "exec/cpu-defs.h" > #include "xtensa-isa.h" > > -#define ALIGNED_ONLY > - > /* Xtensa processors have a weak memory model */ > #define TCG_GUEST_DEFAULT_MO (0) > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index be2c33c..8d23fb0 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -1926,7 +1926,7 @@ static const char * const ldst_name[] = > }; > > static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { > -#ifdef ALIGNED_ONLY > +#ifdef TARGET_ALIGNED_ONLY > [MO_UNALN >> MO_ASHIFT] = "un+", > [MO_ALIGN >> MO_ASHIFT] = "", > #else > diff --git a/tcg/tcg.h b/tcg/tcg.h > index b411e17..529acb2 100644 > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -333,10 +333,12 @@ typedef enum TCGMemOp { > MO_TE = MO_LE, > #endif > > - /* MO_UNALN accesses are never checked for alignment. > + /* > + * MO_UNALN accesses are never checked for alignment. > * MO_ALIGN accesses will result in a call to the CPU's > * do_unaligned_access hook if the guest address is not aligned. > - * The default depends on whether the target CPU defines ALIGNED_ONLY. > + * The default depends on whether the target CPU defines > + * TARGET_ALIGNED_ONLY. > * > * Some architectures (e.g. ARMv8) need the address which is aligned > * to a size more than the size of the memory access. > @@ -353,7 +355,7 @@ typedef enum TCGMemOp { > */ > MO_ASHIFT = 4, > MO_AMASK = 7 << MO_ASHIFT, > -#ifdef ALIGNED_ONLY > +#ifdef TARGET_ALIGNED_ONLY > MO_ALIGN = 0, > MO_UNALN = MO_AMASK, > #else > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2 1/2] configure: Define target access alignment in configure 2019-07-22 3:27 ` [Qemu-devel] [PATCH v2 1/2] " tony.nguyen 2019-07-22 10:54 ` Philippe Mathieu-Daudé @ 2019-07-23 16:18 ` Aleksandar Markovic 1 sibling, 0 replies; 6+ messages in thread From: Aleksandar Markovic @ 2019-07-23 16:18 UTC (permalink / raw) To: tony.nguyen Cc: Eduardo Habkost, Aleksandar Rikalo, Mark Cave-Ayland, QEMU Developers, jcmvbkbc, Artyom Tarasenko, Aleksandar Markovic, Aurelien Jarno, Richard Henderson Hello, Tony On Mon, Jul 22, 2019 at 5:27 AM <tony.nguyen@bt.com> wrote: > Move the define of target access alignment earlier from > target/foo/cpu.h to configure. > > It would be better if the commit message explained WHY the change is needed and HOW it is achieved - not WHAT the change is. Yours, Aleksandar > Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> > --- > configure | 10 +++++++++- > include/exec/poison.h | 1 + > include/qom/cpu.h | 2 +- > target/alpha/cpu.h | 2 -- > target/hppa/cpu.h | 1 - > target/mips/cpu.h | 2 -- > target/sh4/cpu.h | 2 -- > target/sparc/cpu.h | 2 -- > target/xtensa/cpu.h | 2 -- > tcg/tcg.c | 2 +- > tcg/tcg.h | 8 +++++--- > 11 files changed, 17 insertions(+), 17 deletions(-) > > diff --git a/configure b/configure > index eb635c3..8316a16 100755 > --- a/configure > +++ b/configure > @@ -7424,8 +7424,13 @@ for target in $target_list; do > target_dir="$target" > config_target_mak=$target_dir/config-target.mak > target_name=$(echo $target | cut -d '-' -f 1) > +target_aligned_only="no" > +case "$target_name" in > + > alpha|hppa|mips64el|mips64|mipsel|mips|mipsn32|mipsn32el|sh4|sh4eb|sparc|sparc64|sparc32plus|xtensa|xtensaeb) > + target_aligned_only="yes" > + ;; > +esac > target_bigendian="no" > - > case "$target_name" in > > armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb) > target_bigendian=yes > @@ -7710,6 +7715,9 @@ fi > if supported_whpx_target $target; then > echo "CONFIG_WHPX=y" >> $config_target_mak > fi > +if test "$target_aligned_only" = "yes" ; then > + echo "TARGET_ALIGNED_ONLY=y" >> $config_target_mak > +fi > if test "$target_bigendian" = "yes" ; then > echo "TARGET_WORDS_BIGENDIAN=y" >> $config_target_mak > fi > diff --git a/include/exec/poison.h b/include/exec/poison.h > index b862320..955eb86 100644 > --- a/include/exec/poison.h > +++ b/include/exec/poison.h > @@ -35,6 +35,7 @@ > #pragma GCC poison TARGET_UNICORE32 > #pragma GCC poison TARGET_XTENSA > > +#pragma GCC poison TARGET_ALIGNED_ONLY > #pragma GCC poison TARGET_HAS_BFLT > #pragma GCC poison TARGET_NAME > #pragma GCC poison TARGET_SUPPORTS_MTTCG > diff --git a/include/qom/cpu.h b/include/qom/cpu.h > index 5ee0046..9b50b73 100644 > --- a/include/qom/cpu.h > +++ b/include/qom/cpu.h > @@ -89,7 +89,7 @@ struct TranslationBlock; > * @do_unassigned_access: Callback for unassigned access handling. > * (this is deprecated: new targets should use do_transaction_failed > instead) > * @do_unaligned_access: Callback for unaligned access handling, if > - * the target defines #ALIGNED_ONLY. > + * the target defines #TARGET_ALIGNED_ONLY. > * @do_transaction_failed: Callback for handling failed memory > transactions > * (ie bus faults or external aborts; not MMU faults) > * @virtio_is_big_endian: Callback to return %true if a CPU which supports > diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h > index b3e8a82..16eb804 100644 > --- a/target/alpha/cpu.h > +++ b/target/alpha/cpu.h > @@ -23,8 +23,6 @@ > #include "cpu-qom.h" > #include "exec/cpu-defs.h" > > -#define ALIGNED_ONLY > - > /* Alpha processors have a weak memory model */ > #define TCG_GUEST_DEFAULT_MO (0) > > diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h > index aab251b..2be67c2 100644 > --- a/target/hppa/cpu.h > +++ b/target/hppa/cpu.h > @@ -30,7 +30,6 @@ > basis. It's probably easier to fall back to a strong memory model. */ > #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL > > -#define ALIGNED_ONLY > #define MMU_KERNEL_IDX 0 > #define MMU_USER_IDX 3 > #define MMU_PHYS_IDX 4 > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > index 21c0615..c13cd4e 100644 > --- a/target/mips/cpu.h > +++ b/target/mips/cpu.h > @@ -1,8 +1,6 @@ > #ifndef MIPS_CPU_H > #define MIPS_CPU_H > > -#define ALIGNED_ONLY > - > #include "cpu-qom.h" > #include "exec/cpu-defs.h" > #include "fpu/softfloat.h" > diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h > index aee733e..ecaa7a1 100644 > --- a/target/sh4/cpu.h > +++ b/target/sh4/cpu.h > @@ -23,8 +23,6 @@ > #include "cpu-qom.h" > #include "exec/cpu-defs.h" > > -#define ALIGNED_ONLY > - > /* CPU Subtypes */ > #define SH_CPU_SH7750 (1 << 0) > #define SH_CPU_SH7750S (1 << 1) > diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h > index 8ed2250..1406f0b 100644 > --- a/target/sparc/cpu.h > +++ b/target/sparc/cpu.h > @@ -5,8 +5,6 @@ > #include "cpu-qom.h" > #include "exec/cpu-defs.h" > > -#define ALIGNED_ONLY > - > #if !defined(TARGET_SPARC64) > #define TARGET_DPREGS 16 > #else > diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h > index 2c27713..0459243 100644 > --- a/target/xtensa/cpu.h > +++ b/target/xtensa/cpu.h > @@ -32,8 +32,6 @@ > #include "exec/cpu-defs.h" > #include "xtensa-isa.h" > > -#define ALIGNED_ONLY > - > /* Xtensa processors have a weak memory model */ > #define TCG_GUEST_DEFAULT_MO (0) > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index be2c33c..8d23fb0 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -1926,7 +1926,7 @@ static const char * const ldst_name[] = > }; > > static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { > -#ifdef ALIGNED_ONLY > +#ifdef TARGET_ALIGNED_ONLY > [MO_UNALN >> MO_ASHIFT] = "un+", > [MO_ALIGN >> MO_ASHIFT] = "", > #else > diff --git a/tcg/tcg.h b/tcg/tcg.h > index b411e17..529acb2 100644 > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -333,10 +333,12 @@ typedef enum TCGMemOp { > MO_TE = MO_LE, > #endif > > - /* MO_UNALN accesses are never checked for alignment. > + /* > + * MO_UNALN accesses are never checked for alignment. > * MO_ALIGN accesses will result in a call to the CPU's > * do_unaligned_access hook if the guest address is not aligned. > - * The default depends on whether the target CPU defines ALIGNED_ONLY. > + * The default depends on whether the target CPU defines > + * TARGET_ALIGNED_ONLY. > * > * Some architectures (e.g. ARMv8) need the address which is aligned > * to a size more than the size of the memory access. > @@ -353,7 +355,7 @@ typedef enum TCGMemOp { > */ > MO_ASHIFT = 4, > MO_AMASK = 7 << MO_ASHIFT, > -#ifdef ALIGNED_ONLY > +#ifdef TARGET_ALIGNED_ONLY > MO_ALIGN = 0, > MO_UNALN = MO_AMASK, > #else > -- > 1.8.3.1 > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v2 2/2] configure: Cosmetic yes to "yes" for consistency 2019-07-22 3:19 [Qemu-devel] [PATCH v2 0/2] configure: Define target access alignment in configure tony.nguyen 2019-07-22 3:27 ` [Qemu-devel] [PATCH v2 1/2] " tony.nguyen @ 2019-07-22 3:28 ` tony.nguyen 2019-07-23 16:12 ` Aleksandar Markovic 1 sibling, 1 reply; 6+ messages in thread From: tony.nguyen @ 2019-07-22 3:28 UTC (permalink / raw) To: qemu-devel Cc: ehabkost, arikalo, mark.cave-ayland, jcmvbkbc, aurelien, amarkovic, atar4qemu, rth Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index 8316a16..c07687c 100755 --- a/configure +++ b/configure @@ -7433,7 +7433,7 @@ esac target_bigendian="no" case "$target_name" in armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb) - target_bigendian=yes + target_bigendian="yes" ;; esac target_softmmu="no" -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2 2/2] configure: Cosmetic yes to "yes" for consistency 2019-07-22 3:28 ` [Qemu-devel] [PATCH v2 2/2] configure: Cosmetic yes to "yes" for consistency tony.nguyen @ 2019-07-23 16:12 ` Aleksandar Markovic 0 siblings, 0 replies; 6+ messages in thread From: Aleksandar Markovic @ 2019-07-23 16:12 UTC (permalink / raw) To: tony.nguyen Cc: Eduardo Habkost, Aleksandar Rikalo, Mark Cave-Ayland, QEMU Developers, jcmvbkbc, Artyom Tarasenko, Aleksandar Markovic, Aurelien Jarno, Richard Henderson Hi, Tony On Mon, Jul 22, 2019 at 5:28 AM <tony.nguyen@bt.com> wrote: > Signed-off-by: Tony Nguyen <tony.nguyen@bt.com> > --- > configure | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/configure b/configure > index 8316a16..c07687c 100755 > --- a/configure > +++ b/configure > @@ -7433,7 +7433,7 @@ esac > target_bigendian="no" > case "$target_name" in > > armeb|aarch64_be|hppa|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or1k|ppc|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb) > - target_bigendian=yes > + target_bigendian="yes" > ;; > esac > target_softmmu="no" > -- > 1.8.3.1 > > But, there are loads of similar cases (see 'grep "=yes" configure' output) - what do we do to them? Perhaps not all should be corrected in a similar way, but it looks to me that we should not limit this patch to just an individual case. If we do the cleanup, let's do it to be complete or almost complete. The same, of course, goes for "=no", and other variable assignments. Yours, Aleksandar $ grep "=yes" configure export CCACHE_RECACHE=yes git_update=yes --help|-h) show_help=yes --enable-git-update) git_update=yes --enable-debug-mutex) debug_mutex=yes --enable-libpmem) libpmem=yes *"-softmmu "*) softmmu=yes have_broken_size_max=yes l2tpv3=yes test "$vhost_user" = "" && vhost_user=yes test "$vhost_net_user" = "yes" && vhost_net=yes test "$vhost_kernel" = "yes" && vhost_net=yes xen=yes xen=yes xen=yes xen=yes xen=yes xen=yes xen=yes xen=yes xen=yes xen_pci_passthrough=yes sparse=yes have_x11=yes need_x11=yes gcrypt_hmac=yes tasn1=yes auth_pam=yes have_ifaddrs_h=yes sdl=yes sdl_image=yes need_x11=yes vnc_sasl=yes vnc_jpeg=yes vnc_png=yes xkbcommon=yes vde=yes netmap=yes cap_ng=yes brlapi=yes iconv_found=yes iconv=yes curses_found=yes curses=yes curl=yes bluez=yes gio=yes mpathpersist=yes mpathpersist_new_api=yes mpathpersist=yes cap=yes pthread=yes pthread=yes found=yes pthread_setname_np_w_tid=yes pthread_setname_np_wo_tid=yes rbd=yes libssh=yes linux_aio=yes tpm=yes attr=yes attr=yes libattr=yes iovec=yes preadv=yes fdt_required=yes fdt=yes opengl=yes opengl_dmabuf=yes need_x11=yes inotify=yes inotify1=yes pipe2=yes accept4=yes splice=yes numa=yes signalfd=yes optreset=yes eventfd=yes memfd=yes have_usbfs=yes fallocate=yes fallocate_punch_hole=yes fallocate_zero_range=yes posix_fallocate=yes sync_file_range=yes fiemap=yes dup3=yes ppoll=yes prctl_pr_set_timerslack=yes epoll=yes epoll_create1=yes sendfile=yes timerfd=yes setns=yes clock_adjtime=yes syncfs=yes docs=yes byteswap_h=yes bswap_h=yes guest_agent_ntddscsi=yes fdatasync=yes madvise=yes posix_madvise=yes posix_memalign=yes posix_syslog=yes sem_timedwait=yes strchrnul=yes ucontext_works=yes coroutine_pool=yes open_by_handle_at=yes linux_magic_h=yes pragma_diagnostic_available=yes valgrind_h=yes has_environ=yes cpuid_h=yes int128=yes atomic128=yes cmpxchg128=yes atomic64=yes vector16=yes getauxval=yes ccache_cpp2=yes have_copy_file_range=yes have_fsxattr=yes have_membarrier=yes have_membarrier=yes have_rtnetlink=yes have_af_vsock=yes have_afalg=yes have_sysmacros=yes vxhs=yes have_static_assert=yes have_utmpx=yes have_getrandom=yes have_asan=yes have_ubsan=yes have_asan_iface_h=yes have_asan_iface_fiber=yes ivshmem=yes virtfs=yes mpath=yes guest_agent=yes guest_agent_msi=yes echo "QEMU_GA_MSI_ENABLED=yes" >> $config_host_mak echo "BUILD_DOCS=yes" >> $config_host_mak echo "INSTALL_BLOBS=yes" >> $config_host_mak target_bigendian=yes mttcg=yes mttcg=yes mttcg=yes mttcg=yes mttcg=yes ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-07-23 16:18 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-07-22 3:19 [Qemu-devel] [PATCH v2 0/2] configure: Define target access alignment in configure tony.nguyen 2019-07-22 3:27 ` [Qemu-devel] [PATCH v2 1/2] " tony.nguyen 2019-07-22 10:54 ` Philippe Mathieu-Daudé 2019-07-23 16:18 ` Aleksandar Markovic 2019-07-22 3:28 ` [Qemu-devel] [PATCH v2 2/2] configure: Cosmetic yes to "yes" for consistency tony.nguyen 2019-07-23 16:12 ` Aleksandar Markovic
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).