From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmer@sifive.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs
Date: Wed, 7 Aug 2019 00:45:20 -0700 [thread overview]
Message-ID: <1565163924-18621-25-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1565163924-18621-1-git-send-email-bmeng.cn@gmail.com>
The loading of initramfs is currently not supported on 'sifive_u'.
Add the support to make '-initrd' command line parameter useful.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
Changes in v2: None
hw/riscv/sifive_u.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ce6eba5..30e6c43 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -328,7 +328,18 @@ static void riscv_sifive_u_init(MachineState *machine)
memmap[SIFIVE_U_DRAM].base);
if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename);
+ uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename);
+
+ if (machine->initrd_filename) {
+ hwaddr start;
+ hwaddr end = riscv_load_initrd(machine->initrd_filename,
+ machine->ram_size, kernel_entry,
+ &start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen",
+ "linux,initrd-start", start);
+ qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end",
+ end);
+ }
}
/* reset vector */
--
2.7.4
next prev parent reply other threads:[~2019-08-07 7:57 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-07 7:44 [Qemu-devel] [PATCH v2 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-07 7:44 ` [Qemu-devel] [PATCH v2 01/28] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-07 7:44 ` [Qemu-devel] [PATCH v2 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-07 7:44 ` [Qemu-devel] [PATCH v2 03/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-07 9:50 ` Philippe Mathieu-Daudé
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 04/28] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 07/28] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-07 9:46 ` Philippe Mathieu-Daudé
2019-08-07 10:05 ` Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 09/28] riscv: sifive_u: Update UART base addresses Bin Meng
2019-08-07 9:25 ` Chih-Min Chao
2019-08-07 9:38 ` Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-07 8:54 ` Chih-Min Chao
2019-08-07 10:10 ` Bin Meng
2019-08-08 14:00 ` Chih-Min Chao
2019-08-10 1:51 ` Alistair Francis
[not found] ` <CAEUhbmWENVV+DzX756OCUGYc5ES-aCdD8tpSoVoPspniuiGh2A@mail.gmail.com>
2019-08-11 17:06 ` Alistair Francis
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-07 8:59 ` Chih-Min Chao
2019-08-07 9:49 ` Philippe Mathieu-Daudé
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-07 9:00 ` Chih-Min Chao
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 16/28] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 18/28] riscv: hw: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 21/28] riscv: sifive_u: Update UART and ethernet node clock properties Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 22/28] riscv: sifive_u: Generate an aliases node in the device tree Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 23/28] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-07 7:45 ` Bin Meng [this message]
2019-08-07 9:04 ` [Qemu-devel] [PATCH v2 24/28] riscv: sifive_u: Support loading initramfs Chih-Min Chao
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 25/28] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 27/28] riscv: virt: Change create_fdt() to return void Bin Meng
2019-08-07 9:04 ` [Qemu-devel] [Qemu-riscv] " Chih-Min Chao
2019-08-07 9:48 ` [Qemu-devel] " Philippe Mathieu-Daudé
2019-08-07 7:45 ` [Qemu-devel] [PATCH v2 28/28] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
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