From: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>
To: qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com, philmd@redhat.com, amarkovic@wavecomp.com
Subject: [Qemu-devel] [PATCH for 4.2 v7 18/26] target/mips: Clean up handling of CP0 register 2
Date: Fri, 9 Aug 2019 14:46:51 +0200 [thread overview]
Message-ID: <1565354819-1495-19-git-send-email-aleksandar.markovic@rt-rk.com> (raw)
In-Reply-To: <1565354819-1495-1-git-send-email-aleksandar.markovic@rt-rk.com>
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Clean up handling of CP0 register 2.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/cpu.h | 7 ++++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 39 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 597afa8..eebdc9f 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -294,6 +294,13 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
+#define CP0_REG02__TCSTATUS 1
+#define CP0_REG02__TCBIND 2
+#define CP0_REG02__TCRESTART 3
+#define CP0_REG02__TCHALT 4
+#define CP0_REG02__TCCONTEXT 5
+#define CP0_REG02__TCSCHEDULE 6
+#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1
diff --git a/target/mips/translate.c b/target/mips/translate.c
index dad32e9..3fb3757 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6929,7 +6929,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6946,37 +6946,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -7698,41 +7698,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
@@ -8449,41 +8449,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -9170,41 +9170,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_dmtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
--
2.7.4
next prev parent reply other threads:[~2019-08-09 12:56 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-09 12:46 [Qemu-devel] [PATCH for 4.2 v7 00/26] target/mips: Misc patches for 4.2 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 01/26] target/mips: Add support for DSPRAM Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 02/26] target/mips: Amend CP0 WatchHi register implementation Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 03/26] target/mips: Amend CP0 MemoryMapID " Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 04/26] target/mips: Add support for emulation of GINVT instruction Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 05/26] target/mips: Add support for emulation of CRC32 group of instructions Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 06/26] target/mips: Style improvements in cp0_timer.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 07/26] target/mips: Style improvements in cpu.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 08/26] target/mips: Style improvements in helper.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 09/26] target/mips: Style improvements in internal.h Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 10/26] target/mips: Style improvements in machine.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 11/26] target/mips: Style improvements in cps.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 12/26] target/mips: Style improvements in mips_fulong2e.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 13/26] target/mips: Style improvements in mips_int.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 14/26] target/mips: Style improvements in mips_malta.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 15/26] target/mips: Style improvements in mips_mipssim.c Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 16/26] target/mips: Clean up handling of CP0 register 0 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 17/26] target/mips: Clean up handling of CP0 register 1 Aleksandar Markovic
2019-08-09 12:46 ` Aleksandar Markovic [this message]
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 19/26] target/mips: Clean up handling of CP0 register 5 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 20/26] target/mips: Clean up handling of CP0 register 20 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 21/26] target/mips: Clean up handling of CP0 register 24 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 22/26] target/mips: Clean up handling of CP0 register 26 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 23/26] target/mips: Clean up handling of CP0 register 30 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 24/26] target/mips: Clean up handling of CP0 register 31 Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 25/26] target/mips: tests/tcg: Add optional printing of more detailed failure info Aleksandar Markovic
2019-08-09 12:46 ` [Qemu-devel] [PATCH for 4.2 v7 26/26] target/mips: tests/tcg: Fix target configurations for MSA tests Aleksandar Markovic
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1565354819-1495-19-git-send-email-aleksandar.markovic@rt-rk.com \
--to=aleksandar.markovic@rt-rk.com \
--cc=amarkovic@wavecomp.com \
--cc=arikalo@wavecomp.com \
--cc=philmd@redhat.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).