From: "Paul A. Clarke" <pc@us.ibm.com>
To: david@gibson.dropbear.id.au
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH] ppc: Fix xsmaddmdp and friends
Date: Wed, 21 Aug 2019 10:28:41 -0500 [thread overview]
Message-ID: <1566401321-22419-1-git-send-email-pc@us.ibm.com> (raw)
From: "Paul A. Clarke" <pc@us.ibm.com>
A class of instructions of the form:
op Target,A,B
which operate like:
Target = Target * A + B
have a bit set which distinguishes them from instructions that operate as:
Target = Target * B + A
This bit is not being checked properly (using PPC_BIT macro), so all
instructions in this class are operating incorrectly as the second form
above. The bit was being checked as if it were part of a 64-bit
instruction opcode, rather than a proper 32-bit opcode. Fix by using the
macro (PPC_BIT32) which treats the opcode as a 32-bit quantity.
Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
---
target/ppc/translate/vsx-impl.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 3922686..8287e27 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1308,7 +1308,7 @@ static void gen_##name(DisasContext *ctx) \
} \
xt = gen_vsr_ptr(xT(ctx->opcode)); \
xa = gen_vsr_ptr(xA(ctx->opcode)); \
- if (ctx->opcode & PPC_BIT(25)) { \
+ if (ctx->opcode & PPC_BIT32(25)) { \
/* \
* AxT + B \
*/ \
--
1.8.3.1
next reply other threads:[~2019-08-21 15:29 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-21 15:28 Paul A. Clarke [this message]
2019-08-21 22:56 ` [Qemu-devel] [PATCH] ppc: Fix xsmaddmdp and friends David Gibson
2019-08-28 17:32 ` [Qemu-devel] [Qemu-ppc] " Laurent Vivier
2019-08-28 23:28 ` David Gibson
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