* [PATCH 01/11] target/mips: Clean up helper.c
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 02/11] target/mips: Clean up internal.h Aleksandar Markovic
` (9 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.c | 132 +++++++++++++++++++++++++++++++--------------------
1 file changed, 80 insertions(+), 52 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index a2b6459..3dd1aae 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -39,8 +39,8 @@ enum {
#if !defined(CONFIG_USER_ONLY)
/* no MMU emulation */
-int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type)
+int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type)
{
*physical = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
}
/* fixed mapping MMU emulation */
-int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type)
+int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
- if (!(env->CP0_Status & (1 << CP0St_ERL)))
+ if (!(env->CP0_Status & (1 << CP0St_ERL))) {
*physical = address + 0x40000000UL;
- else
+ } else {
*physical = address;
- } else if (address <= (int32_t)0xBFFFFFFFUL)
+ }
+ } else if (address <= (int32_t)0xBFFFFFFFUL) {
*physical = address & 0x1FFFFFFF;
- else
+ } else {
*physical = address;
+ }
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type)
+int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type)
{
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
int i;
@@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
*physical = tlb->PFN[n] | (address & (mask >> 1));
*prot = PAGE_READ;
- if (n ? tlb->D1 : tlb->D0)
+ if (n ? tlb->D1 : tlb->D0) {
*prot |= PAGE_WRITE;
+ }
if (!(n ? tlb->XI1 : tlb->XI0)) {
*prot |= PAGE_EXEC;
}
@@ -130,8 +133,11 @@ static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
int32_t adetlb_mask;
switch (mmu_idx) {
- case 3 /* ERL */:
- /* If EU is set, always unmapped */
+ case 3:
+ /*
+ * ERL
+ * If EU is set, always unmapped
+ */
if (eu) {
return 0;
}
@@ -204,9 +210,9 @@ static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
pa & ~(hwaddr)segmask);
}
-static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
- int *prot, target_ulong real_address,
- int rw, int access_type, int mmu_idx)
+static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
+ int *prot, target_ulong real_address,
+ int rw, int access_type, int mmu_idx)
{
/* User mode can only access useg/xuseg */
#if defined(TARGET_MIPS64)
@@ -252,14 +258,15 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
} else {
segctl = env->CP0_SegCtl2 >> 16;
}
- ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
- access_type, mmu_idx, segctl,
- 0x3FFFFFFF);
+ ret = get_segctl_physical_address(env, physical, prot,
+ real_address, rw, access_type,
+ mmu_idx, segctl, 0x3FFFFFFF);
#if defined(TARGET_MIPS64)
} else if (address < 0x4000000000000000ULL) {
/* xuseg */
if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
+ ret = env->tlb->map_address(env, physical, prot,
+ real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -267,7 +274,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
/* xsseg */
if ((supervisor_mode || kernel_mode) &&
SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
+ ret = env->tlb->map_address(env, physical, prot,
+ real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -307,7 +315,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
/* xkseg */
if (kernel_mode && KX &&
address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
+ ret = env->tlb->map_address(env, physical, prot,
+ real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -328,8 +337,10 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
access_type, mmu_idx,
env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
} else {
- /* kseg3 */
- /* XXX: debug segment is not emulated */
+ /*
+ * kseg3
+ * XXX: debug segment is not emulated
+ */
ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
access_type, mmu_idx,
env->CP0_SegCtl0, 0x1FFFFFFF);
@@ -515,9 +526,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
#if defined(TARGET_MIPS64)
env->CP0_EntryHi &= env->SEGMask;
env->CP0_XContext =
- /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
- /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
- /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
+ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
+ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */
+ (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */
#endif
cs->exception_index = exception;
env->error_code = error_code;
@@ -945,7 +956,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
#ifndef CONFIG_USER_ONLY
-hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
+hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
+ int rw)
{
hwaddr physical;
int prot;
@@ -1005,7 +1017,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
};
#endif
-target_ulong exception_resume_pc (CPUMIPSState *env)
+target_ulong exception_resume_pc(CPUMIPSState *env)
{
target_ulong bad_pc;
target_ulong isa_mode;
@@ -1013,8 +1025,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
bad_pc = env->active_tc.PC | isa_mode;
if (env->hflags & MIPS_HFLAG_BMASK) {
- /* If the exception was raised from a delay slot, come back to
- the jump. */
+ /*
+ * If the exception was raised from a delay slot, come back to
+ * the jump.
+ */
bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
}
@@ -1022,14 +1036,14 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
}
#if !defined(CONFIG_USER_ONLY)
-static void set_hflags_for_handler (CPUMIPSState *env)
+static void set_hflags_for_handler(CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */
env->hflags &= ~(MIPS_HFLAG_M16);
/* ...except that microMIPS lets you choose. */
if (env->insn_flags & ASE_MICROMIPS) {
- env->hflags |= (!!(env->CP0_Config3
- & (1 << CP0C3_ISA_ON_EXC))
+ env->hflags |= (!!(env->CP0_Config3 &
+ (1 << CP0C3_ISA_ON_EXC))
<< MIPS_HFLAG_M16_SHIFT);
}
}
@@ -1096,10 +1110,12 @@ void mips_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
- /* Debug single step cannot be raised inside a delay slot and
- resume will always occur on the next instruction
- (but we assume the pc has always been updated during
- code translation). */
+ /*
+ * Debug single step cannot be raised inside a delay slot and
+ * resume will always occur on the next instruction
+ * (but we assume the pc has always been updated during
+ * code translation).
+ */
env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
goto enter_debug_mode;
case EXCP_DINT:
@@ -1111,7 +1127,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
case EXCP_DBp:
env->CP0_Debug |= 1 << CP0DB_DBp;
/* Setup DExcCode - SDBBP instruction */
- env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
+ env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
+ (9 << CP0DB_DEC);
goto set_DEPC;
case EXCP_DDBS:
env->CP0_Debug |= 1 << CP0DB_DDBS;
@@ -1132,8 +1149,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
/* EJTAG probe trap enable is not implemented... */
- if (!(env->CP0_Status & (1 << CP0St_EXL)))
+ if (!(env->CP0_Status & (1 << CP0St_EXL))) {
env->CP0_Cause &= ~(1U << CP0Ca_BD);
+ }
env->active_tc.PC = env->exception_base + 0x480;
set_hflags_for_handler(env);
break;
@@ -1159,8 +1177,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
}
env->hflags |= MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
- if (!(env->CP0_Status & (1 << CP0St_EXL)))
+ if (!(env->CP0_Status & (1 << CP0St_EXL))) {
env->CP0_Cause &= ~(1U << CP0Ca_BD);
+ }
env->active_tc.PC = env->exception_base;
set_hflags_for_handler(env);
break;
@@ -1176,12 +1195,16 @@ void mips_cpu_do_interrupt(CPUState *cs)
uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
- /* For VEIC mode, the external interrupt controller feeds
- * the vector through the CP0Cause IP lines. */
+ /*
+ * For VEIC mode, the external interrupt controller feeds
+ * the vector through the CP0Cause IP lines.
+ */
vector = pending;
} else {
- /* Vectored Interrupts
- * Mask with Status.IM7-IM0 to get enabled interrupts. */
+ /*
+ * Vectored Interrupts
+ * Mask with Status.IM7-IM0 to get enabled interrupts.
+ */
pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
/* Find the highest-priority interrupt. */
while (pending >>= 1) {
@@ -1354,7 +1377,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->active_tc.PC += offset;
set_hflags_for_handler(env);
- env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
+ env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
+ (cause << CP0Ca_EC);
break;
default:
abort();
@@ -1390,7 +1414,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
#if !defined(CONFIG_USER_ONLY)
-void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
+void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
{
CPUState *cs = env_cpu(env);
r4k_tlb_t *tlb;
@@ -1400,16 +1424,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
target_ulong mask;
tlb = &env->tlb->mmu.r4k.tlb[idx];
- /* The qemu TLB is flushed when the ASID changes, so no need to
- flush these entries again. */
+ /*
+ * The qemu TLB is flushed when the ASID changes, so no need to
+ * flush these entries again.
+ */
if (tlb->G == 0 && tlb->ASID != ASID) {
return;
}
if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
- /* For tlbwr, we can shadow the discarded entry into
- a new (fake) TLB entry, as long as the guest can not
- tell that it's there. */
+ /*
+ * For tlbwr, we can shadow the discarded entry into
+ * a new (fake) TLB entry, as long as the guest can not
+ * tell that it's there.
+ */
env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
env->tlb->tlb_in_use++;
return;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 02/11] target/mips: Clean up internal.h
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 01/11] target/mips: Clean up helper.c Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 03/11] target/mips: Clean up kvm_mips.h Aleksandar Markovic
` (8 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/internal.h | 60 +++++++++++++++++++++++++++++++-------------------
1 file changed, 37 insertions(+), 23 deletions(-)
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 685e8d6..3f435b5 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -1,4 +1,5 @@
-/* mips internal definitions and helpers
+/*
+ * MIPS internal definitions and helpers
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@@ -9,8 +10,10 @@
#include "fpu/softfloat-helpers.h"
-/* MMU types, the first four entries have the same layout as the
- CP0C0_MT field. */
+/*
+ * MMU types, the first four entries have the same layout as the
+ * CP0C0_MT field.
+ */
enum mips_mmu_types {
MMU_TYPE_NONE,
MMU_TYPE_R4000,
@@ -160,9 +163,11 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM) &&
- /* Note that the TCStatus IXMT field is initialized to zero,
- and only MT capable cores can set it to one. So we don't
- need to check for MT capabilities here. */
+ /*
+ * Note that the TCStatus IXMT field is initialized to zero,
+ * and only MT capable cores can set it to one. So we don't
+ * need to check for MT capabilities here.
+ */
!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
}
@@ -177,14 +182,18 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
status = env->CP0_Status & CP0Ca_IP_mask;
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
- /* A MIPS configured with a vectorizing external interrupt controller
- will feed a vector into the Cause pending lines. The core treats
- the status lines as a vector level, not as indiviual masks. */
+ /*
+ * A MIPS configured with a vectorizing external interrupt controller
+ * will feed a vector into the Cause pending lines. The core treats
+ * the status lines as a vector level, not as indiviual masks.
+ */
r = pending > status;
} else {
- /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
- treats the pending lines as individual interrupt lines, the status
- lines are individual masks. */
+ /*
+ * A MIPS configured with compatibility or VInt (Vectored Interrupts)
+ * treats the pending lines as individual interrupt lines, the status
+ * lines are individual masks.
+ */
r = (pending & status) != 0;
}
return r;
@@ -275,12 +284,14 @@ static inline int mips_vpe_active(CPUMIPSState *env)
active = 0;
}
- /* Now verify that there are active thread contexts in the VPE.
-
- This assumes the CPU model will internally reschedule threads
- if the active one goes to sleep. If there are no threads available
- the active one will be in a sleeping state, and we can turn off
- the entire VPE. */
+ /*
+ * Now verify that there are active thread contexts in the VPE.
+ *
+ * This assumes the CPU model will internally reschedule threads
+ * if the active one goes to sleep. If there are no threads available
+ * the active one will be in a sleeping state, and we can turn off
+ * the entire VPE.
+ */
if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
/* TC is not activated. */
active = 0;
@@ -326,7 +337,8 @@ static inline void compute_hflags(CPUMIPSState *env)
if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM)) {
- env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
+ env->hflags |= (env->CP0_Status >> CP0St_KSU) &
+ MIPS_HFLAG_KSU;
}
#if defined(TARGET_MIPS64)
if ((env->insn_flags & ISA_MIPS3) &&
@@ -403,10 +415,12 @@ static inline void compute_hflags(CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_COP1X;
}
} else if (env->insn_flags & ISA_MIPS4) {
- /* All supported MIPS IV CPUs use the XX (CU3) to enable
- and disable the MIPS IV extensions to the MIPS III ISA.
- Some other MIPS IV CPUs ignore the bit, so the check here
- would be too restrictive for them. */
+ /*
+ * All supported MIPS IV CPUs use the XX (CU3) to enable
+ * and disable the MIPS IV extensions to the MIPS III ISA.
+ * Some other MIPS IV CPUs ignore the bit, so the check here
+ * would be too restrictive for them.
+ */
if (env->CP0_Status & (1U << CP0St_CU3)) {
env->hflags |= MIPS_HFLAG_COP1X;
}
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 03/11] target/mips: Clean up kvm_mips.h
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 01/11] target/mips: Clean up helper.c Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 02/11] target/mips: Clean up internal.h Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 04/11] target/mips: Clean up mips-defs.h Aleksandar Markovic
` (7 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/kvm_mips.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/kvm_mips.h b/target/mips/kvm_mips.h
index ae957f3..1e40147 100644
--- a/target/mips/kvm_mips.h
+++ b/target/mips/kvm_mips.h
@@ -7,7 +7,7 @@
*
* Copyright (C) 2012-2014 Imagination Technologies Ltd.
* Authors: Sanjay Lal <sanjayl@kymasys.com>
-*/
+ */
#ifndef KVM_MIPS_H
#define KVM_MIPS_H
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 04/11] target/mips: Clean up mips-defs.h
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (2 preceding siblings ...)
2019-09-24 13:26 ` [PATCH 03/11] target/mips: Clean up kvm_mips.h Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 05/11] target/mips: Clean up op_helper.c Aleksandar Markovic
` (6 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/mips-defs.h | 53 ++++++++++++++++++++++++++-----------------------
1 file changed, 28 insertions(+), 25 deletions(-)
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index bbf056a..938c0de 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -2,7 +2,7 @@
#define QEMU_MIPS_DEFS_H
/* If we want to use host float regs... */
-//#define USE_HOST_FLOAT_REGS
+/* #define USE_HOST_FLOAT_REGS */
/* Real pages are variable size... */
#define MIPS_TLB_MAX 128
@@ -57,43 +57,46 @@
#define ASE_MXU 0x0200000000000000ULL
/* MIPS CPU defines. */
-#define CPU_MIPS1 (ISA_MIPS1)
-#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
-#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
-#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
-#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
-#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
-#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
-#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
+#define CPU_MIPS1 (ISA_MIPS1)
+#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2)
+#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3)
+#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4)
+#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX)
+#define CPU_R5900 (CPU_MIPS3 | INSN_R5900)
+#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E)
+#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F)
-#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
+#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5)
/* MIPS Technologies "Release 1" */
-#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
-#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
+#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32)
+#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64)
/* MIPS Technologies "Release 2" */
-#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
-#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
+#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2)
+#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2)
/* MIPS Technologies "Release 3" */
-#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
-#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+#define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3 | ISA_MIPS64R3)
/* MIPS Technologies "Release 5" */
-#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
-#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+#define CPU_MIPS64R5 (CPU_MIPS64R3 | CPU_MIPS32R5 | ISA_MIPS64R5)
/* MIPS Technologies "Release 6" */
-#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
-#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
+#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
+#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
/* Wave Computing: "nanoMIPS" */
-#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
+#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
-/* Strictly follow the architecture standard:
- - Disallow "special" instruction handling for PMON/SPIM.
- Note that we still maintain Count/Compare to match the host clock. */
-//#define MIPS_STRICT_STANDARD 1
+/*
+ * Strictly follow the architecture standard:
+ * - Disallow "special" instruction handling for PMON/SPIM.
+ * Note that we still maintain Count/Compare to match the host clock.
+ *
+ * #define MIPS_STRICT_STANDARD 1
+ */
#endif /* QEMU_MIPS_DEFS_H */
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 05/11] target/mips: Clean up op_helper.c
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (3 preceding siblings ...)
2019-09-24 13:26 ` [PATCH 04/11] target/mips: Clean up mips-defs.h Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 06/11] target/mips: Clean up translate.c Aleksandar Markovic
` (5 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/op_helper.c | 913 ++++++++++++++++++++++++++++++++----------------
1 file changed, 606 insertions(+), 307 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 4de6465..beca781 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -64,8 +64,7 @@ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
int mem_idx, uintptr_t retaddr) \
{ \
- switch (mem_idx) \
- { \
+ switch (mem_idx) { \
case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
default: \
@@ -92,8 +91,7 @@ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
type val, int mem_idx, uintptr_t retaddr) \
{ \
- switch (mem_idx) \
- { \
+ switch (mem_idx) { \
case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
default: \
@@ -535,7 +533,7 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
target_ulong i;
for (i = 0; i < base_reglist; i++) {
@@ -557,7 +555,7 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
target_ulong i;
for (i = 0; i < base_reglist; i++) {
@@ -579,7 +577,7 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
target_ulong i;
for (i = 0; i < base_reglist; i++) {
@@ -600,7 +598,7 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
target_ulong i;
for (i = 0; i < base_reglist; i++) {
@@ -623,8 +621,10 @@ static bool mips_vpe_is_wfi(MIPSCPU *c)
CPUState *cpu = CPU(c);
CPUMIPSState *env = &c->env;
- /* If the VPE is halted but otherwise active, it means it's waiting for
- an interrupt. */
+ /*
+ * If the VPE is halted but otherwise active, it means it's waiting for
+ * an interrupt.\
+ */
return cpu->halted && mips_vpe_active(env);
}
@@ -638,9 +638,11 @@ static bool mips_vp_is_wfi(MIPSCPU *c)
static inline void mips_vpe_wake(MIPSCPU *c)
{
- /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
- because there might be other conditions that state that c should
- be sleeping. */
+ /*
+ * Don't set ->halted = 0 directly, let it be done via cpu_has_work
+ * because there might be other conditions that state that c should
+ * be sleeping.
+ */
qemu_mutex_lock_iothread();
cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
qemu_mutex_unlock_iothread();
@@ -650,8 +652,10 @@ static inline void mips_vpe_sleep(MIPSCPU *cpu)
{
CPUState *cs = CPU(cpu);
- /* The VPE was shut off, really go to bed.
- Reset any old _WAKE requests. */
+ /*
+ * The VPE was shut off, really go to bed.
+ * Reset any old _WAKE requests.
+ */
cs->halted = 1;
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
}
@@ -684,9 +688,12 @@ static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
* This function will transform @tc into a local index within the
* returned #CPUMIPSState.
*/
-/* FIXME: This code assumes that all VPEs have the same number of TCs,
- which depends on runtime setup. Can probably be fixed by
- walking the list of CPUMIPSStates. */
+
+/*
+ * FIXME: This code assumes that all VPEs have the same number of TCs,
+ * which depends on runtime setup. Can probably be fixed by
+ * walking the list of CPUMIPSStates.
+ */
static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
{
MIPSCPU *cpu;
@@ -712,17 +719,21 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
return &cpu->env;
}
-/* The per VPE CP0_Status register shares some fields with the per TC
- CP0_TCStatus registers. These fields are wired to the same registers,
- so changes to either of them should be reflected on both registers.
-
- Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
-
- These helper call synchronizes the regs for a given cpu. */
+/*
+ * The per VPE CP0_Status register shares some fields with the per TC
+ * CP0_TCStatus registers. These fields are wired to the same registers,
+ * so changes to either of them should be reflected on both registers.
+ *
+ * Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
+ *
+ * These helper call synchronizes the regs for a given cpu.
+ */
-/* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
-/* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
- int tc); */
+/*
+ * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c.
+ * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
+ * int tc);
+ */
/* Called for updates to CP0_TCStatus. */
static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
@@ -805,10 +816,11 @@ target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCStatus;
- else
+ } else {
return other->tcs[other_tc].CP0_TCStatus;
+ }
}
target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
@@ -821,10 +833,11 @@ target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCBind;
- else
+ } else {
return other->tcs[other_tc].CP0_TCBind;
+ }
}
target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
@@ -837,10 +850,11 @@ target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.PC;
- else
+ } else {
return other->tcs[other_tc].PC;
+ }
}
target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
@@ -853,10 +867,11 @@ target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCHalt;
- else
+ } else {
return other->tcs[other_tc].CP0_TCHalt;
+ }
}
target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
@@ -869,10 +884,11 @@ target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCContext;
- else
+ } else {
return other->tcs[other_tc].CP0_TCContext;
+ }
}
target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
@@ -885,10 +901,11 @@ target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCSchedule;
- else
+ } else {
return other->tcs[other_tc].CP0_TCSchedule;
+ }
}
target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
@@ -901,10 +918,11 @@ target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCScheFBack;
- else
+ } else {
return other->tcs[other_tc].CP0_TCScheFBack;
+ }
}
target_ulong helper_mfc0_count(CPUMIPSState *env)
@@ -987,8 +1005,9 @@ target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
target_ulong helper_mfc0_debug(CPUMIPSState *env)
{
target_ulong t0 = env->CP0_Debug;
- if (env->hflags & MIPS_HFLAG_DM)
+ if (env->hflags & MIPS_HFLAG_DM) {
t0 |= 1 << CP0DB_DM;
+ }
return t0;
}
@@ -999,10 +1018,11 @@ target_ulong helper_mftc0_debug(CPUMIPSState *env)
int32_t tcstatus;
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
tcstatus = other->active_tc.CP0_Debug_tcstatus;
- else
+ } else {
tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
+ }
/* XXX: Might be wrong, check with EJTAG spec. */
return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
@@ -1076,14 +1096,16 @@ void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
uint32_t mask = 0;
uint32_t newval;
- if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
+ if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
(1 << CP0MVPCo_EVP);
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ }
+ if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0MVPCo_STLB);
+ }
newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
- // TODO: Enable/disable shared TLB, enable/disable VPEs.
+ /* TODO: Enable/disable shared TLB, enable/disable VPEs. */
env->mvp->CP0_MVPControl = newval;
}
@@ -1097,10 +1119,12 @@ void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
(1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
- /* Yield scheduler intercept not implemented. */
- /* Gating storage scheduler intercept not implemented. */
+ /*
+ * Yield scheduler intercept not implemented.
+ * Gating storage scheduler intercept not implemented.
+ */
- // TODO: Enable/disable TCs.
+ /* TODO: Enable/disable TCs. */
env->CP0_VPEControl = newval;
}
@@ -1143,13 +1167,14 @@ void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
uint32_t newval;
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
- if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
+ if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) {
mask |= (0xff << CP0VPEC0_XTC);
+ }
mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
}
newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
- // TODO: TC exclusive handling due to ERL/EXL.
+ /* TODO: TC exclusive handling due to ERL/EXL. */
env->CP0_VPEConf0 = newval;
}
@@ -1181,7 +1206,7 @@ void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
/* UDI not implemented. */
/* CP2 not implemented. */
- // TODO: Handle FPU (CP1) binding.
+ /* TODO: Handle FPU (CP1) binding. */
env->CP0_VPEConf1 = newval;
}
@@ -1233,10 +1258,11 @@ void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCStatus = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCStatus = arg1;
+ }
sync_c0_tcstatus(other, other_tc, arg1);
}
@@ -1245,8 +1271,9 @@ void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
env->active_tc.CP0_TCBind = newval;
}
@@ -1258,8 +1285,9 @@ void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
uint32_t newval;
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
if (other_tc == other->current_tc) {
newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
other->active_tc.CP0_TCBind = newval;
@@ -1304,7 +1332,7 @@ void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
env->active_tc.CP0_TCHalt = arg1 & 0x1;
- // TODO: Halt TC / Restart (if allocated+active) TC.
+ /* TODO: Halt TC / Restart (if allocated+active) TC. */
if (env->active_tc.CP0_TCHalt & 1) {
mips_tc_sleep(cpu, env->current_tc);
} else {
@@ -1318,12 +1346,13 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
MIPSCPU *other_cpu = env_archcpu(other);
- // TODO: Halt TC / Restart (if allocated+active) TC.
+ /* TODO: Halt TC / Restart (if allocated+active) TC. */
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCHalt = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCHalt = arg1;
+ }
if (arg1 & 1) {
mips_tc_sleep(other_cpu, other_tc);
@@ -1342,10 +1371,11 @@ void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCContext = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCContext = arg1;
+ }
}
void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
@@ -1358,10 +1388,11 @@ void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCSchedule = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCSchedule = arg1;
+ }
}
void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
@@ -1374,10 +1405,11 @@ void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCScheFBack = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCScheFBack = arg1;
+ }
}
void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
@@ -1703,9 +1735,15 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
case 3:
qemu_log(", ERL\n");
break;
- case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
- case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
- case MIPS_HFLAG_KM: qemu_log("\n"); break;
+ case MIPS_HFLAG_UM:
+ qemu_log(", UM\n");
+ break;
+ case MIPS_HFLAG_SM:
+ qemu_log(", SM\n");
+ break;
+ case MIPS_HFLAG_KM:
+ qemu_log("\n");
+ break;
default:
cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
break;
@@ -1899,10 +1937,11 @@ void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
- if (arg1 & (1 << CP0DB_DM))
+ if (arg1 & (1 << CP0DB_DM)) {
env->hflags |= MIPS_HFLAG_DM;
- else
+ } else {
env->hflags &= ~MIPS_HFLAG_DM;
+ }
}
void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
@@ -1912,10 +1951,11 @@ void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
/* XXX: Might be wrong, check with EJTAG spec. */
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_Debug_tcstatus = val;
- else
+ } else {
other->tcs[other_tc].CP0_Debug_tcstatus = val;
+ }
other->CP0_Debug = (other->CP0_Debug &
((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
(arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
@@ -1974,10 +2014,11 @@ target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.gpr[sel];
- else
+ } else {
return other->tcs[other_tc].gpr[sel];
+ }
}
target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
@@ -1985,10 +2026,11 @@ target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.LO[sel];
- else
+ } else {
return other->tcs[other_tc].LO[sel];
+ }
}
target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
@@ -1996,10 +2038,11 @@ target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.HI[sel];
- else
+ } else {
return other->tcs[other_tc].HI[sel];
+ }
}
target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
@@ -2007,10 +2050,11 @@ target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.ACX[sel];
- else
+ } else {
return other->tcs[other_tc].ACX[sel];
+ }
}
target_ulong helper_mftdsp(CPUMIPSState *env)
@@ -2018,10 +2062,11 @@ target_ulong helper_mftdsp(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.DSPControl;
- else
+ } else {
return other->tcs[other_tc].DSPControl;
+ }
}
void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
@@ -2029,10 +2074,11 @@ void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.gpr[sel] = arg1;
- else
+ } else {
other->tcs[other_tc].gpr[sel] = arg1;
+ }
}
void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
@@ -2040,10 +2086,11 @@ void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.LO[sel] = arg1;
- else
+ } else {
other->tcs[other_tc].LO[sel] = arg1;
+ }
}
void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
@@ -2051,10 +2098,11 @@ void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.HI[sel] = arg1;
- else
+ } else {
other->tcs[other_tc].HI[sel] = arg1;
+ }
}
void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
@@ -2062,10 +2110,11 @@ void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.ACX[sel] = arg1;
- else
+ } else {
other->tcs[other_tc].ACX[sel] = arg1;
+ }
}
void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
@@ -2073,22 +2122,23 @@ void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.DSPControl = arg1;
- else
+ } else {
other->tcs[other_tc].DSPControl = arg1;
+ }
}
/* MIPS MT functions */
target_ulong helper_dmt(void)
{
- // TODO
- return 0;
+ /* TODO */
+ return 0;
}
target_ulong helper_emt(void)
{
- // TODO
+ /* TODO */
return 0;
}
@@ -2130,8 +2180,10 @@ target_ulong helper_evpe(CPUMIPSState *env)
void helper_fork(target_ulong arg1, target_ulong arg2)
{
- // arg1 = rt, arg2 = rs
- // TODO: store to TC register
+ /*
+ * arg1 = rt, arg2 = rs
+ * TODO: store to TC register
+ */
}
target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
@@ -2149,11 +2201,12 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
}
}
} else if (arg1 == 0) {
- if (0 /* TODO: TC underflow */) {
+ if (0) {
+ /* TODO: TC underflow */
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
do_raise_exception(env, EXCP_THREAD, GETPC());
} else {
- // TODO: Deallocate TC
+ /* TODO: Deallocate TC */
}
} else if (arg1 > 0) {
/* Yield qualifier inputs not implemented. */
@@ -2193,8 +2246,10 @@ target_ulong helper_evp(CPUMIPSState *env)
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
- /* If the VP is WFI, don't disturb its sleep.
- * Otherwise, wake it up. */
+ /*
+ * If the VP is WFI, don't disturb its sleep.
+ * Otherwise, wake it up.
+ */
mips_vpe_wake(other_cpu);
}
}
@@ -2206,7 +2261,7 @@ target_ulong helper_evp(CPUMIPSState *env)
#ifndef CONFIG_USER_ONLY
/* TLB management */
-static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
+static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first)
{
/* Discard entries from env->tlb[first] onwards. */
while (env->tlb->tlb_in_use > first) {
@@ -2308,8 +2363,10 @@ void r4k_helper_tlbwi(CPUMIPSState *env)
XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
- /* Discard cached TLB entries, unless tlbwi is just upgrading access
- permissions on the current entry. */
+ /*
+ * Discard cached TLB entries, unless tlbwi is just upgrading access
+ * permissions on the current entry.
+ */
if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
(!tlb->EHINV && EHINV) ||
(tlb->V0 && !V0) || (tlb->D0 && !D0) ||
@@ -2370,7 +2427,7 @@ void r4k_helper_tlbp(CPUMIPSState *env)
#endif
/* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
- r4k_mips_tlb_flush_extra (env, i);
+ r4k_mips_tlb_flush_extra(env, i);
break;
}
}
@@ -2400,8 +2457,9 @@ void r4k_helper_tlbr(CPUMIPSState *env)
tlb = &env->tlb->mmu.r4k.tlb[idx];
/* If this will change the current ASID, flush qemu's TLB. */
- if (ASID != tlb->ASID)
+ if (ASID != tlb->ASID) {
cpu_mips_tlb_flush(env);
+ }
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
@@ -2476,10 +2534,12 @@ static void debug_pre_eret(CPUMIPSState *env)
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
- if (env->CP0_Status & (1 << CP0St_ERL))
+ if (env->CP0_Status & (1 << CP0St_ERL)) {
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
- if (env->hflags & MIPS_HFLAG_DM)
+ }
+ if (env->hflags & MIPS_HFLAG_DM) {
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
+ }
qemu_log("\n");
}
}
@@ -2489,17 +2549,25 @@ static void debug_post_eret(CPUMIPSState *env)
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
- if (env->CP0_Status & (1 << CP0St_ERL))
+ if (env->CP0_Status & (1 << CP0St_ERL)) {
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
- if (env->hflags & MIPS_HFLAG_DM)
+ }
+ if (env->hflags & MIPS_HFLAG_DM) {
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
+ }
switch (cpu_mmu_index(env, false)) {
case 3:
qemu_log(", ERL\n");
break;
- case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
- case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
- case MIPS_HFLAG_KM: qemu_log("\n"); break;
+ case MIPS_HFLAG_UM:
+ qemu_log(", UM\n");
+ break;
+ case MIPS_HFLAG_SM:
+ qemu_log(", SM\n");
+ break;
+ case MIPS_HFLAG_KM:
+ qemu_log("\n");
+ break;
default:
cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
break;
@@ -2609,8 +2677,9 @@ void helper_pmon(CPUMIPSState *env, int function)
function /= 2;
switch (function) {
case 2: /* TODO: char inbyte(int waitflag); */
- if (env->active_tc.gpr[4] == 0)
+ if (env->active_tc.gpr[4] == 0) {
env->active_tc.gpr[2] = -1;
+ }
/* Fall through */
case 11: /* TODO: char inbyte (void); */
env->active_tc.gpr[2] = -1;
@@ -2636,8 +2705,10 @@ void helper_wait(CPUMIPSState *env)
cs->halted = 1;
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
- /* Last instruction in the block, PC was updated before
- - no need to recover PC and icount */
+ /*
+ * Last instruction in the block, PC was updated before
+ * - no need to recover PC and icount.
+ */
raise_exception(env, EXCP_HLT);
}
@@ -2731,13 +2802,15 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
}
break;
case 25:
- arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
+ arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) |
+ ((env->active_fpu.fcr31 >> 23) & 0x1);
break;
case 26:
arg1 = env->active_fpu.fcr31 & 0x0003f07c;
break;
case 28:
- arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
+ arg1 = (env->active_fpu.fcr31 & 0x00000f83) |
+ ((env->active_fpu.fcr31 >> 22) & 0x4);
break;
default:
arg1 = (int32_t)env->active_fpu.fcr31;
@@ -2802,19 +2875,24 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
return;
}
- env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
- ((arg1 & 0x1) << 23);
+ env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) |
+ ((arg1 & 0xfe) << 24) |
+ ((arg1 & 0x1) << 23);
break;
case 26:
- if (arg1 & 0x007c0000)
+ if (arg1 & 0x007c0000) {
return;
- env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
+ }
+ env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) |
+ (arg1 & 0x0003f07c);
break;
case 28:
- if (arg1 & 0x007c0000)
+ if (arg1 & 0x007c0000) {
return;
- env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
- ((arg1 & 0x4) << 22);
+ }
+ env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) |
+ (arg1 & 0x00000f83) |
+ ((arg1 & 0x4) << 22);
break;
case 31:
env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
@@ -2828,8 +2906,10 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
}
restore_fp_status(env);
set_float_exception_flags(0, &env->active_fpu.fp_status);
- if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
+ if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) &
+ GET_FP_CAUSE(env->active_fpu.fcr31)) {
do_raise_exception(env, EXCP_FPE, GETPC());
+ }
}
int ieee_ex_to_mips(int xcpt)
@@ -2857,7 +2937,8 @@ int ieee_ex_to_mips(int xcpt)
static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
{
- int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
+ int tmp = ieee_ex_to_mips(get_float_exception_flags(
+ &env->active_fpu.fp_status));
SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
@@ -2872,10 +2953,12 @@ static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
}
}
-/* Float support.
- Single precition routines have a "s" suffix, double precision a
- "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
- paired single lower "pl", paired single upper "pu". */
+/*
+ * Float support.
+ * Single precition routines have a "s" suffix, double precision a
+ * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
+ * paired single lower "pl", paired single upper "pu".
+ */
/* unary operations, modifying fp status */
uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
@@ -3056,7 +3139,8 @@ uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
- set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
@@ -3071,7 +3155,8 @@ uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
- set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
@@ -3086,7 +3171,8 @@ uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
- set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
@@ -3101,7 +3187,8 @@ uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
- set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
@@ -3116,7 +3203,8 @@ uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
- dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
+ dt2 = float64_to_int64_round_to_zero(fdt0,
+ &env->active_fpu.fp_status);
if (get_float_exception_flags(&env->active_fpu.fp_status)
& (float_flag_invalid | float_flag_overflow)) {
dt2 = FP_TO_INT64_OVERFLOW;
@@ -3860,7 +3948,8 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
{
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
+ fst2 = float32_chs(float32_sub(fst2, float32_one,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return fst2;
}
@@ -3874,8 +3963,10 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
- fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
+ fst2 = float32_chs(float32_sub(fst2, float32_one,
+ &env->active_fpu.fp_status));
+ fsth2 = float32_chs(float32_sub(fsth2, float32_one,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
}
@@ -3884,7 +3975,8 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
- fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
+ fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return fdt2;
}
@@ -3893,7 +3985,8 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
{
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
+ fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return fst2;
}
@@ -3909,8 +4002,10 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
- fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
+ fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
+ &env->active_fpu.fp_status));
+ fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
}
@@ -3924,8 +4019,8 @@ uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
uint32_t fst2;
uint32_t fsth2;
- fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
+ fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
}
@@ -3939,8 +4034,8 @@ uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
uint32_t fst2;
uint32_t fsth2;
- fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
+ fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
}
@@ -4072,26 +4167,58 @@ void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
CLEAR_FP_COND(cc, env->active_fpu); \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float64_unordered_quiet() is still called. */
-FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
-FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
-FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float64_unordered() is still called. */
-FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
-FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
-FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float64_unordered_quiet() is still called.
+ */
+FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status))
+FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_eq_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float64_unordered() is still called.
+ */
+FOP_COND_D(sf, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_D(ngle, float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status))
+FOP_COND_D(seq, float64_eq(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ngl, float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_eq(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(lt, float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(nge, float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(le, float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ngt, float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status))
#define FOP_COND_S(op, cond) \
void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
@@ -4119,26 +4246,58 @@ void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
CLEAR_FP_COND(cc, env->active_fpu); \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered_quiet() is still called. */
-FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
-FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
-FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered() is still called. */
-FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
-FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
-FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered_quiet() is still called.
+ */
+FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_S(un, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status))
+FOP_COND_S(eq, float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(olt, float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ole, float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered() is still called.
+ */
+FOP_COND_S(sf, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_S(ngle, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status))
+FOP_COND_S(seq, float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ngl, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(lt, float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(nge, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(le, float32_le(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ngt, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le(fst0, fst1,
+ &env->active_fpu.fp_status))
#define FOP_COND_PS(op, condl, condh) \
void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
@@ -4184,42 +4343,102 @@ void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
CLEAR_FP_COND(cc + 1, env->active_fpu); \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered_quiet() is still called. */
-FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
- (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
-FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
- float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
-FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered() is still called. */
-FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
- (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
-FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
- float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
-FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
- float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
- float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
- float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered_quiet() is still called.
+ */
+FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status), 0),
+ (float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status),
+ float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_eq_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_eq_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_lt_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ole, float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_le_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered() is still called.
+ */
+FOP_COND_PS(sf, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status), 0),
+ (float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_PS(ngle, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status),
+ float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(seq, float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_eq(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ngl, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_eq(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(lt, float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_lt(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(nge, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(le, float32_le(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_le(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ngt, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_le(fsth0, fsth1,
+ &env->active_fpu.fp_status))
/* R6 compare operations */
#define FOP_CONDN_D(op, cond) \
@@ -4236,46 +4455,86 @@ uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
} \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float64_unordered_quiet() is still called. */
-FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
-FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
-FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float64_unordered() is still called. */
-FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
-FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
-FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float64_unordered_quiet() is still called.
+ */
+FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status), 0))
+FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_eq_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float64_unordered() is still called.\
+ */
+FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status), 0))
+FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_eq(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sle, (float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sor, (float64_le(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
#define FOP_CONDN_S(op, cond) \
uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
@@ -4291,46 +4550,86 @@ uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
} \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered_quiet() is still called. */
-FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
-FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
-FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered() is still called. */
-FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
-FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
-FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
- || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
- || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
- || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered_quiet() is still called.
+ */
+FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status), 0))
+FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered() is still called.
+ */
+FOP_CONDN_S(saf, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status), 0))
+FOP_CONDN_S(sun, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(seq, (float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(slt, (float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sult, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sle, (float32_le(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sule, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sor, (float32_le(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sune, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sne, (float32_lt(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status)))
/* MSA */
/* Data format min and max values */
@@ -4522,7 +4821,7 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
}
#define MSA_PAGESPAN(x) \
- ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
+ ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
static inline void ensure_writable_pages(CPUMIPSState *env,
target_ulong addr,
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 06/11] target/mips: Clean up translate.c
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (4 preceding siblings ...)
2019-09-24 13:26 ` [PATCH 05/11] target/mips: Clean up op_helper.c Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:51 ` Philippe Mathieu-Daudé
2019-09-24 13:26 ` [PATCH 07/11] target/mips: msa: Split helpers for <NLOC|NLZC>.<B|H|W|D> Aleksandar Markovic
` (4 subsequent siblings)
10 siblings, 1 reply; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/translate.c | 30 ++++++++++++++++++------------
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index f211995..cc5af2a 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -7118,7 +7118,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
tcg_gen_andi_tl(arg, arg, ~0xffff);
register_name = "BadInstrX";
break;
- default:
+ default:
goto cp0_unimplemented;
}
break;
@@ -7545,7 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
- offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
+ offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
tcg_gen_ext32s_tl(arg, arg);
register_name = "KScratch";
break;
@@ -8295,7 +8295,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
- offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
+ offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch";
break;
default:
@@ -8387,17 +8387,20 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
+ tcg_gen_ld_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
+ tcg_gen_ld_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
+ tcg_gen_ld_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
@@ -8412,7 +8415,8 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_02:
switch (sel) {
case CP0_REG02__ENTRYLO0:
- tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
+ tcg_gen_ld_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
case CP0_REG02__TCSTATUS:
@@ -8756,7 +8760,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
- /* 6,7 are implementation dependent */
+ /* 6,7 are implementation dependent */
case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
@@ -8837,7 +8841,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
break;
case CP0_REGISTER_21:
- /* Officially reserved, but sel 0 is used for R1x000 framemask */
+ /* Officially reserved, but sel 0 is used for R1x000 framemask */
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
switch (sel) {
case 0:
@@ -9022,7 +9026,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
- offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
+ offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
register_name = "KScratch";
break;
default:
@@ -9112,12 +9116,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
+ tcg_gen_st_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
- tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
+ tcg_gen_st_tl(arg, cpu_env,
+ offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
case CP0_REG01__VPEOPT:
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 06/11] target/mips: Clean up translate.c
2019-09-24 13:26 ` [PATCH 06/11] target/mips: Clean up translate.c Aleksandar Markovic
@ 2019-09-24 13:51 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 13+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-09-24 13:51 UTC (permalink / raw)
To: Aleksandar Markovic, qemu-devel; +Cc: arikalo
On 9/24/19 3:26 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 30 ++++++++++++++++++------------
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index f211995..cc5af2a 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -7118,7 +7118,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> tcg_gen_andi_tl(arg, arg, ~0xffff);
> register_name = "BadInstrX";
> break;
> - default:
> + default:
> goto cp0_unimplemented;
> }
> break;
> @@ -7545,7 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case CP0_REG31__KSCRATCH6:
> CP0_CHECK(ctx->kscrexist & (1 << sel));
> tcg_gen_ld_tl(arg, cpu_env,
> - offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
> tcg_gen_ext32s_tl(arg, arg);
> register_name = "KScratch";
> break;
> @@ -8295,7 +8295,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case CP0_REG31__KSCRATCH6:
> CP0_CHECK(ctx->kscrexist & (1 << sel));
> tcg_gen_st_tl(arg, cpu_env,
> - offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
> register_name = "KScratch";
> break;
> default:
> @@ -8387,17 +8387,20 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> break;
> case CP0_REG01__YQMASK:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
> + tcg_gen_ld_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_YQMask));
> register_name = "YQMask";
> break;
> case CP0_REG01__VPESCHEDULE:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
> + tcg_gen_ld_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_VPESchedule));
> register_name = "VPESchedule";
> break;
> case CP0_REG01__VPESCHEFBACK:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
> + tcg_gen_ld_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_VPEScheFBack));
> register_name = "VPEScheFBack";
> break;
> case CP0_REG01__VPEOPT:
> @@ -8412,7 +8415,8 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case CP0_REGISTER_02:
> switch (sel) {
> case CP0_REG02__ENTRYLO0:
> - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
> + tcg_gen_ld_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_EntryLo0));
> register_name = "EntryLo0";
> break;
> case CP0_REG02__TCSTATUS:
> @@ -8756,7 +8760,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
> register_name = "Config5";
> break;
> - /* 6,7 are implementation dependent */
> + /* 6,7 are implementation dependent */
> case CP0_REG16__CONFIG6:
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
> register_name = "Config6";
> @@ -8837,7 +8841,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> }
> break;
> case CP0_REGISTER_21:
> - /* Officially reserved, but sel 0 is used for R1x000 framemask */
> + /* Officially reserved, but sel 0 is used for R1x000 framemask */
> CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
> switch (sel) {
> case 0:
> @@ -9022,7 +9026,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case CP0_REG31__KSCRATCH6:
> CP0_CHECK(ctx->kscrexist & (1 << sel));
> tcg_gen_ld_tl(arg, cpu_env,
> - offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
> register_name = "KScratch";
> break;
> default:
> @@ -9112,12 +9116,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> break;
> case CP0_REG01__VPESCHEDULE:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
> + tcg_gen_st_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_VPESchedule));
> register_name = "VPESchedule";
> break;
> case CP0_REG01__VPESCHEFBACK:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
> + tcg_gen_st_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_VPEScheFBack));
> register_name = "VPEScheFBack";
> break;
> case CP0_REG01__VPEOPT:
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 07/11] target/mips: msa: Split helpers for <NLOC|NLZC>.<B|H|W|D>
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (5 preceding siblings ...)
2019-09-24 13:26 ` [PATCH 06/11] target/mips: Clean up translate.c Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 08/11] target/mips: msa: Split helpers for PCNT.<B|H|W|D> Aleksandar Markovic
` (3 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 14 +++-
target/mips/msa_helper.c | 170 +++++++++++++++++++++++++++++++++++++++--------
target/mips/translate.c | 30 ++++++++-
3 files changed, 181 insertions(+), 33 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 51f0e1c..d709083 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -777,6 +777,18 @@ DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env)
DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env)
/* MIPS SIMD Architecture */
+
+DEF_HELPER_3(msa_nloc_b, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_h, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_w, void, env, i32, i32)
+DEF_HELPER_3(msa_nloc_d, void, env, i32, i32)
+
+DEF_HELPER_3(msa_nlzc_b, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)
+DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)
+
+
DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32)
@@ -935,8 +947,6 @@ DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index f24061e..8c27c1b 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -65,7 +65,147 @@
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Bit Count group helpers here */
+static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
+{
+ uint64_t x, y;
+ int n, c;
+
+ x = UNSIGNED(arg, df);
+ n = DF_BITS(df);
+ c = DF_BITS(df) / 2;
+
+ do {
+ y = x >> c;
+ if (y != 0) {
+ n = n - c;
+ x = y;
+ }
+ c = c >> 1;
+ } while (c != 0);
+
+ return n - x;
+}
+
+static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
+{
+ return msa_nlzc_df(df, UNSIGNED((~arg), df));
+}
+
+void helper_msa_nloc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->b[0] = msa_nloc_df(DF_BYTE, pws->b[0]);
+ pwd->b[1] = msa_nloc_df(DF_BYTE, pws->b[1]);
+ pwd->b[2] = msa_nloc_df(DF_BYTE, pws->b[2]);
+ pwd->b[3] = msa_nloc_df(DF_BYTE, pws->b[3]);
+ pwd->b[4] = msa_nloc_df(DF_BYTE, pws->b[4]);
+ pwd->b[5] = msa_nloc_df(DF_BYTE, pws->b[5]);
+ pwd->b[6] = msa_nloc_df(DF_BYTE, pws->b[6]);
+ pwd->b[7] = msa_nloc_df(DF_BYTE, pws->b[7]);
+ pwd->b[8] = msa_nloc_df(DF_BYTE, pws->b[8]);
+ pwd->b[9] = msa_nloc_df(DF_BYTE, pws->b[9]);
+ pwd->b[10] = msa_nloc_df(DF_BYTE, pws->b[10]);
+ pwd->b[11] = msa_nloc_df(DF_BYTE, pws->b[11]);
+ pwd->b[12] = msa_nloc_df(DF_BYTE, pws->b[12]);
+ pwd->b[13] = msa_nloc_df(DF_BYTE, pws->b[13]);
+ pwd->b[14] = msa_nloc_df(DF_BYTE, pws->b[14]);
+ pwd->b[15] = msa_nloc_df(DF_BYTE, pws->b[15]);
+}
+
+void helper_msa_nloc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->h[0] = msa_nloc_df(DF_HALF, pws->h[0]);
+ pwd->h[1] = msa_nloc_df(DF_HALF, pws->h[1]);
+ pwd->h[2] = msa_nloc_df(DF_HALF, pws->h[2]);
+ pwd->h[3] = msa_nloc_df(DF_HALF, pws->h[3]);
+ pwd->h[4] = msa_nloc_df(DF_HALF, pws->h[4]);
+ pwd->h[5] = msa_nloc_df(DF_HALF, pws->h[5]);
+ pwd->h[6] = msa_nloc_df(DF_HALF, pws->h[6]);
+ pwd->h[7] = msa_nloc_df(DF_HALF, pws->h[7]);
+}
+
+void helper_msa_nloc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->w[0] = msa_nloc_df(DF_WORD, pws->w[0]);
+ pwd->w[1] = msa_nloc_df(DF_WORD, pws->w[1]);
+ pwd->w[2] = msa_nloc_df(DF_WORD, pws->w[2]);
+ pwd->w[3] = msa_nloc_df(DF_WORD, pws->w[3]);
+}
+
+void helper_msa_nloc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->d[0] = msa_nloc_df(DF_DOUBLE, pws->d[0]);
+ pwd->d[1] = msa_nloc_df(DF_DOUBLE, pws->d[1]);
+}
+
+void helper_msa_nlzc_b(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->b[0] = msa_nlzc_df(DF_BYTE, pws->b[0]);
+ pwd->b[1] = msa_nlzc_df(DF_BYTE, pws->b[1]);
+ pwd->b[2] = msa_nlzc_df(DF_BYTE, pws->b[2]);
+ pwd->b[3] = msa_nlzc_df(DF_BYTE, pws->b[3]);
+ pwd->b[4] = msa_nlzc_df(DF_BYTE, pws->b[4]);
+ pwd->b[5] = msa_nlzc_df(DF_BYTE, pws->b[5]);
+ pwd->b[6] = msa_nlzc_df(DF_BYTE, pws->b[6]);
+ pwd->b[7] = msa_nlzc_df(DF_BYTE, pws->b[7]);
+ pwd->b[8] = msa_nlzc_df(DF_BYTE, pws->b[8]);
+ pwd->b[9] = msa_nlzc_df(DF_BYTE, pws->b[9]);
+ pwd->b[10] = msa_nlzc_df(DF_BYTE, pws->b[10]);
+ pwd->b[11] = msa_nlzc_df(DF_BYTE, pws->b[11]);
+ pwd->b[12] = msa_nlzc_df(DF_BYTE, pws->b[12]);
+ pwd->b[13] = msa_nlzc_df(DF_BYTE, pws->b[13]);
+ pwd->b[14] = msa_nlzc_df(DF_BYTE, pws->b[14]);
+ pwd->b[15] = msa_nlzc_df(DF_BYTE, pws->b[15]);
+}
+
+void helper_msa_nlzc_h(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->h[0] = msa_nlzc_df(DF_HALF, pws->h[0]);
+ pwd->h[1] = msa_nlzc_df(DF_HALF, pws->h[1]);
+ pwd->h[2] = msa_nlzc_df(DF_HALF, pws->h[2]);
+ pwd->h[3] = msa_nlzc_df(DF_HALF, pws->h[3]);
+ pwd->h[4] = msa_nlzc_df(DF_HALF, pws->h[4]);
+ pwd->h[5] = msa_nlzc_df(DF_HALF, pws->h[5]);
+ pwd->h[6] = msa_nlzc_df(DF_HALF, pws->h[6]);
+ pwd->h[7] = msa_nlzc_df(DF_HALF, pws->h[7]);
+}
+
+void helper_msa_nlzc_w(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->w[0] = msa_nlzc_df(DF_WORD, pws->w[0]);
+ pwd->w[1] = msa_nlzc_df(DF_WORD, pws->w[1]);
+ pwd->w[2] = msa_nlzc_df(DF_WORD, pws->w[2]);
+ pwd->w[3] = msa_nlzc_df(DF_WORD, pws->w[3]);
+}
+
+void helper_msa_nlzc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->d[0] = msa_nlzc_df(DF_DOUBLE, pws->d[0]);
+ pwd->d[1] = msa_nlzc_df(DF_DOUBLE, pws->d[1]);
+}
/*
@@ -2524,32 +2664,6 @@ static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
return x;
}
-static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg)
-{
- uint64_t x, y;
- int n, c;
-
- x = UNSIGNED(arg, df);
- n = DF_BITS(df);
- c = DF_BITS(df) / 2;
-
- do {
- y = x >> c;
- if (y != 0) {
- n = n - c;
- x = y;
- }
- c = c >> 1;
- } while (c != 0);
-
- return n - x;
-}
-
-static inline int64_t msa_nloc_df(uint32_t df, int64_t arg)
-{
- return msa_nlzc_df(df, UNSIGNED((~arg), df));
-}
-
void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t rs)
{
@@ -2633,8 +2747,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
} \
}
-MSA_UNOP_DF(nlzc)
-MSA_UNOP_DF(nloc)
MSA_UNOP_DF(pcnt)
#undef MSA_UNOP_DF
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cc5af2a..6de4609 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28962,10 +28962,36 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws);
break;
case OPC_NLOC_df:
- gen_helper_msa_nloc_df(cpu_env, tdf, twd, tws);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_nloc_b(cpu_env, twd, tws);
+ break;
+ case DF_HALF:
+ gen_helper_msa_nloc_h(cpu_env, twd, tws);
+ break;
+ case DF_WORD:
+ gen_helper_msa_nloc_w(cpu_env, twd, tws);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_nloc_d(cpu_env, twd, tws);
+ break;
+ }
break;
case OPC_NLZC_df:
- gen_helper_msa_nlzc_df(cpu_env, tdf, twd, tws);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_nlzc_b(cpu_env, twd, tws);
+ break;
+ case DF_HALF:
+ gen_helper_msa_nlzc_h(cpu_env, twd, tws);
+ break;
+ case DF_WORD:
+ gen_helper_msa_nlzc_w(cpu_env, twd, tws);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_nlzc_d(cpu_env, twd, tws);
+ break;
+ }
break;
default:
MIPS_INVAL("MSA instruction");
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 08/11] target/mips: msa: Split helpers for PCNT.<B|H|W|D>
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (6 preceding siblings ...)
2019-09-24 13:26 ` [PATCH 07/11] target/mips: msa: Split helpers for <NLOC|NLZC>.<B|H|W|D> Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 09/11] target/mips: msa: Split helpers for BINS<L|R>.<B|H|W|D> Aleksandar Markovic
` (2 subsequent siblings)
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 6 +-
target/mips/msa_helper.c | 143 ++++++++++++++++++++++++-----------------------
target/mips/translate.c | 19 ++++++-
3 files changed, 95 insertions(+), 73 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index d709083..18e4c7a 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -788,6 +788,11 @@ DEF_HELPER_3(msa_nlzc_h, void, env, i32, i32)
DEF_HELPER_3(msa_nlzc_w, void, env, i32, i32)
DEF_HELPER_3(msa_nlzc_d, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_b, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32)
+DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32)
+
DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
@@ -946,7 +951,6 @@ DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 8c27c1b..fe27efc 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -207,6 +207,80 @@ void helper_msa_nlzc_d(CPUMIPSState *env, uint32_t wd, uint32_t ws)
pwd->d[1] = msa_nlzc_df(DF_DOUBLE, pws->d[1]);
}
+static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
+{
+ uint64_t x;
+
+ x = UNSIGNED(arg, df);
+
+ x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
+ x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
+ x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
+ x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
+ x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
+ x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
+
+ return x;
+}
+
+void helper_msa_pcnt_b(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->b[0] = msa_pcnt_df(DF_BYTE, pws->b[0]);
+ pwd->b[1] = msa_pcnt_df(DF_BYTE, pws->b[1]);
+ pwd->b[2] = msa_pcnt_df(DF_BYTE, pws->b[2]);
+ pwd->b[3] = msa_pcnt_df(DF_BYTE, pws->b[3]);
+ pwd->b[4] = msa_pcnt_df(DF_BYTE, pws->b[4]);
+ pwd->b[5] = msa_pcnt_df(DF_BYTE, pws->b[5]);
+ pwd->b[6] = msa_pcnt_df(DF_BYTE, pws->b[6]);
+ pwd->b[7] = msa_pcnt_df(DF_BYTE, pws->b[7]);
+ pwd->b[8] = msa_pcnt_df(DF_BYTE, pws->b[8]);
+ pwd->b[9] = msa_pcnt_df(DF_BYTE, pws->b[9]);
+ pwd->b[10] = msa_pcnt_df(DF_BYTE, pws->b[10]);
+ pwd->b[11] = msa_pcnt_df(DF_BYTE, pws->b[11]);
+ pwd->b[12] = msa_pcnt_df(DF_BYTE, pws->b[12]);
+ pwd->b[13] = msa_pcnt_df(DF_BYTE, pws->b[13]);
+ pwd->b[14] = msa_pcnt_df(DF_BYTE, pws->b[14]);
+ pwd->b[15] = msa_pcnt_df(DF_BYTE, pws->b[15]);
+}
+
+void helper_msa_pcnt_h(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->h[0] = msa_pcnt_df(DF_HALF, pws->h[0]);
+ pwd->h[1] = msa_pcnt_df(DF_HALF, pws->h[1]);
+ pwd->h[2] = msa_pcnt_df(DF_HALF, pws->h[2]);
+ pwd->h[3] = msa_pcnt_df(DF_HALF, pws->h[3]);
+ pwd->h[4] = msa_pcnt_df(DF_HALF, pws->h[4]);
+ pwd->h[5] = msa_pcnt_df(DF_HALF, pws->h[5]);
+ pwd->h[6] = msa_pcnt_df(DF_HALF, pws->h[6]);
+ pwd->h[7] = msa_pcnt_df(DF_HALF, pws->h[7]);
+}
+
+void helper_msa_pcnt_w(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->w[0] = msa_pcnt_df(DF_WORD, pws->w[0]);
+ pwd->w[1] = msa_pcnt_df(DF_WORD, pws->w[1]);
+ pwd->w[2] = msa_pcnt_df(DF_WORD, pws->w[2]);
+ pwd->w[3] = msa_pcnt_df(DF_WORD, pws->w[3]);
+}
+
+void helper_msa_pcnt_d(CPUMIPSState *env, uint32_t wd, uint32_t ws)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+
+ pwd->d[0] = msa_pcnt_df(DF_DOUBLE, pws->d[0]);
+ pwd->d[1] = msa_pcnt_df(DF_DOUBLE, pws->d[1]);
+}
+
/*
* Bit Move
@@ -2648,22 +2722,6 @@ void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
msa_move_v(pwd, pws);
}
-static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg)
-{
- uint64_t x;
-
- x = UNSIGNED(arg, df);
-
- x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL);
- x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL);
- x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL);
- x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL);
- x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL);
- x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32));
-
- return x;
-}
-
void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t rs)
{
@@ -2696,59 +2754,6 @@ void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
}
}
-#define MSA_UNOP_DF(func) \
-void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
- uint32_t wd, uint32_t ws) \
-{ \
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
- wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
- \
- switch (df) { \
- case DF_BYTE: \
- pwd->b[0] = msa_ ## func ## _df(df, pws->b[0]); \
- pwd->b[1] = msa_ ## func ## _df(df, pws->b[1]); \
- pwd->b[2] = msa_ ## func ## _df(df, pws->b[2]); \
- pwd->b[3] = msa_ ## func ## _df(df, pws->b[3]); \
- pwd->b[4] = msa_ ## func ## _df(df, pws->b[4]); \
- pwd->b[5] = msa_ ## func ## _df(df, pws->b[5]); \
- pwd->b[6] = msa_ ## func ## _df(df, pws->b[6]); \
- pwd->b[7] = msa_ ## func ## _df(df, pws->b[7]); \
- pwd->b[8] = msa_ ## func ## _df(df, pws->b[8]); \
- pwd->b[9] = msa_ ## func ## _df(df, pws->b[9]); \
- pwd->b[10] = msa_ ## func ## _df(df, pws->b[10]); \
- pwd->b[11] = msa_ ## func ## _df(df, pws->b[11]); \
- pwd->b[12] = msa_ ## func ## _df(df, pws->b[12]); \
- pwd->b[13] = msa_ ## func ## _df(df, pws->b[13]); \
- pwd->b[14] = msa_ ## func ## _df(df, pws->b[14]); \
- pwd->b[15] = msa_ ## func ## _df(df, pws->b[15]); \
- break; \
- case DF_HALF: \
- pwd->h[0] = msa_ ## func ## _df(df, pws->h[0]); \
- pwd->h[1] = msa_ ## func ## _df(df, pws->h[1]); \
- pwd->h[2] = msa_ ## func ## _df(df, pws->h[2]); \
- pwd->h[3] = msa_ ## func ## _df(df, pws->h[3]); \
- pwd->h[4] = msa_ ## func ## _df(df, pws->h[4]); \
- pwd->h[5] = msa_ ## func ## _df(df, pws->h[5]); \
- pwd->h[6] = msa_ ## func ## _df(df, pws->h[6]); \
- pwd->h[7] = msa_ ## func ## _df(df, pws->h[7]); \
- break; \
- case DF_WORD: \
- pwd->w[0] = msa_ ## func ## _df(df, pws->w[0]); \
- pwd->w[1] = msa_ ## func ## _df(df, pws->w[1]); \
- pwd->w[2] = msa_ ## func ## _df(df, pws->w[2]); \
- pwd->w[3] = msa_ ## func ## _df(df, pws->w[3]); \
- break; \
- case DF_DOUBLE: \
- pwd->d[0] = msa_ ## func ## _df(df, pws->d[0]); \
- pwd->d[1] = msa_ ## func ## _df(df, pws->d[1]); \
- break; \
- default: \
- assert(0); \
- } \
-}
-
-MSA_UNOP_DF(pcnt)
-#undef MSA_UNOP_DF
#define FLOAT_ONE32 make_float32(0x3f8 << 20)
#define FLOAT_ONE64 make_float64(0x3ffULL << 52)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6de4609..0d06ba9 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28958,9 +28958,6 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
#endif
gen_helper_msa_fill_df(cpu_env, tdf, twd, tws); /* trs */
break;
- case OPC_PCNT_df:
- gen_helper_msa_pcnt_df(cpu_env, tdf, twd, tws);
- break;
case OPC_NLOC_df:
switch (df) {
case DF_BYTE:
@@ -28993,6 +28990,22 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_PCNT_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_pcnt_b(cpu_env, twd, tws);
+ break;
+ case DF_HALF:
+ gen_helper_msa_pcnt_h(cpu_env, twd, tws);
+ break;
+ case DF_WORD:
+ gen_helper_msa_pcnt_w(cpu_env, twd, tws);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_pcnt_d(cpu_env, twd, tws);
+ break;
+ }
+ break;
default:
MIPS_INVAL("MSA instruction");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 09/11] target/mips: msa: Split helpers for BINS<L|R>.<B|H|W|D>
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (7 preceding siblings ...)
2019-09-24 13:26 ` [PATCH 08/11] target/mips: msa: Split helpers for PCNT.<B|H|W|D> Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 10/11] target/mips: msa: Unroll loops and demacro <BMNZ|BMZ|BSEL>.V Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 11/11] target/mips: msa: Split helpers for B<CLR|NEG|SEL>.<B|H|W|D> Aleksandar Markovic
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 10 +++
target/mips/msa_helper.c | 198 +++++++++++++++++++++++++++++++++++++++--------
target/mips/translate.c | 38 +++++++--
3 files changed, 206 insertions(+), 40 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 18e4c7a..9349482 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -793,6 +793,16 @@ DEF_HELPER_3(msa_pcnt_h, void, env, i32, i32)
DEF_HELPER_3(msa_pcnt_w, void, env, i32, i32)
DEF_HELPER_3(msa_pcnt_d, void, env, i32, i32)
+DEF_HELPER_4(msa_binsl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsl_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_binsr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index fe27efc..7c9da99 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -301,7 +301,170 @@ void helper_msa_pcnt_d(CPUMIPSState *env, uint32_t wd, uint32_t ws)
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Bit Move group helpers here */
+/* Data format bit position and unsigned values */
+#define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
+
+static inline int64_t msa_binsl_df(uint32_t df,
+ int64_t dest, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t u_dest = UNSIGNED(dest, df);
+ int32_t sh_d = BIT_POSITION(arg2, df) + 1;
+ int32_t sh_a = DF_BITS(df) - sh_d;
+ if (sh_d == DF_BITS(df)) {
+ return u_arg1;
+ } else {
+ return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
+ UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
+ }
+}
+
+void helper_msa_binsl_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[1]);
+ pwd->b[2] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[2]);
+ pwd->b[3] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[3]);
+ pwd->b[4] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[4]);
+ pwd->b[5] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[5]);
+ pwd->b[6] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[6]);
+ pwd->b[7] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[7]);
+ pwd->b[8] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[8]);
+ pwd->b[9] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[9]);
+ pwd->b[10] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[10]);
+ pwd->b[11] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[11]);
+ pwd->b[12] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[12]);
+ pwd->b[13] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[13]);
+ pwd->b[14] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[14]);
+ pwd->b[15] = msa_binsl_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[15]);
+}
+
+void helper_msa_binsl_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[1]);
+ pwd->h[2] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[2]);
+ pwd->h[3] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[3]);
+ pwd->h[4] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[4]);
+ pwd->h[5] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[5]);
+ pwd->h[6] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[6]);
+ pwd->h[7] = msa_binsl_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[7]);
+}
+
+void helper_msa_binsl_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[1]);
+ pwd->w[2] = msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[2]);
+ pwd->w[3] = msa_binsl_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[3]);
+}
+
+void helper_msa_binsl_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_binsl_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_binsl_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[1]);
+}
+
+static inline int64_t msa_binsr_df(uint32_t df,
+ int64_t dest, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t u_dest = UNSIGNED(dest, df);
+ int32_t sh_d = BIT_POSITION(arg2, df) + 1;
+ int32_t sh_a = DF_BITS(df) - sh_d;
+ if (sh_d == DF_BITS(df)) {
+ return u_arg1;
+ } else {
+ return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
+ UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
+ }
+}
+
+void helper_msa_binsr_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[1]);
+ pwd->b[2] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[2]);
+ pwd->b[3] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[3]);
+ pwd->b[4] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[4]);
+ pwd->b[5] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[5]);
+ pwd->b[6] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[6]);
+ pwd->b[7] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[7]);
+ pwd->b[8] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[8]);
+ pwd->b[9] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[9]);
+ pwd->b[10] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[10]);
+ pwd->b[11] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[11]);
+ pwd->b[12] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[12]);
+ pwd->b[13] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[13]);
+ pwd->b[14] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[14]);
+ pwd->b[15] = msa_binsr_df(DF_BYTE, pwd->b[0], pws->b[0], pwt->b[15]);
+}
+
+void helper_msa_binsr_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[1]);
+ pwd->h[2] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[2]);
+ pwd->h[3] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[3]);
+ pwd->h[4] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[4]);
+ pwd->h[5] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[5]);
+ pwd->h[6] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[6]);
+ pwd->h[7] = msa_binsr_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[7]);
+}
+
+void helper_msa_binsr_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[1]);
+ pwd->w[2] = msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[2]);
+ pwd->w[3] = msa_binsr_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[3]);
+}
+
+void helper_msa_binsr_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[1]);
+}
/*
@@ -1023,9 +1186,6 @@ void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
}
}
-/* Data format bit position and unsigned values */
-#define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df))
-
static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int32_t b_arg2 = BIT_POSITION(arg2, df);
@@ -1064,36 +1224,6 @@ static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
}
-static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t u_dest = UNSIGNED(dest, df);
- int32_t sh_d = BIT_POSITION(arg2, df) + 1;
- int32_t sh_a = DF_BITS(df) - sh_d;
- if (sh_d == DF_BITS(df)) {
- return u_arg1;
- } else {
- return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) |
- UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df);
- }
-}
-
-static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1,
- int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t u_dest = UNSIGNED(dest, df);
- int32_t sh_d = BIT_POSITION(arg2, df) + 1;
- int32_t sh_a = DF_BITS(df) - sh_d;
- if (sh_d == DF_BITS(df)) {
- return u_arg1;
- } else {
- return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) |
- UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df);
- }
-}
-
static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
{
return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) :
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 0d06ba9..6080c72 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28386,6 +28386,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
TCGv_i32 twt = tcg_const_i32(wt);
switch (MASK_MSA_3R(ctx->opcode)) {
+ case OPC_BINSL_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_BINSR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_SLL_df:
gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28515,9 +28547,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_ILVR_df:
gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_BINSL_df:
- gen_helper_msa_binsl_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_MAX_A_df:
gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28530,9 +28559,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_ILVEV_df:
gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_BINSR_df:
- gen_helper_msa_binsr_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_MIN_A_df:
gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 10/11] target/mips: msa: Unroll loops and demacro <BMNZ|BMZ|BSEL>.V
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (8 preceding siblings ...)
2019-09-24 13:26 ` [PATCH 09/11] target/mips: msa: Split helpers for BINS<L|R>.<B|H|W|D> Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 11/11] target/mips: msa: Split helpers for B<CLR|NEG|SEL>.<B|H|W|D> Aleksandar Markovic
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 7 +++---
target/mips/msa_helper.c | 63 ++++++++++++++++++++++++++++++------------------
2 files changed, 43 insertions(+), 27 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 9349482..27544a1 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -803,6 +803,10 @@ DEF_HELPER_4(msa_binsr_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_binsr_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_binsr_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
@@ -957,9 +961,6 @@ DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
-DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_fill_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 7c9da99..eda675a 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -466,6 +466,42 @@ void helper_msa_binsr_d(CPUMIPSState *env,
pwd->d[1] = msa_binsr_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[1]);
}
+void helper_msa_bmnz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = UNSIGNED( \
+ ((pwd->d[0] & (~pwt->d[0])) | (pws->d[0] & pwt->d[0])), DF_DOUBLE);
+ pwd->d[1] = UNSIGNED( \
+ ((pwd->d[1] & (~pwt->d[1])) | (pws->d[1] & pwt->d[1])), DF_DOUBLE);
+}
+
+void helper_msa_bmz_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = UNSIGNED( \
+ ((pwd->d[0] & pwt->d[0]) | (pws->d[0] & (~pwt->d[0]))), DF_DOUBLE);
+ pwd->d[1] = UNSIGNED( \
+ ((pwd->d[1] & pwt->d[1]) | (pws->d[1] & (~pwt->d[1]))), DF_DOUBLE);
+}
+
+void helper_msa_bsel_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = UNSIGNED( \
+ (pws->d[0] & (~pwd->d[0])) | (pwt->d[0] & pwd->d[0]), DF_DOUBLE);
+ pwd->d[1] = UNSIGNED( \
+ (pws->d[1] & (~pwd->d[1])) | (pwt->d[1] & pwd->d[1]), DF_DOUBLE);
+}
+
/*
* Bit Set
@@ -946,6 +982,9 @@ MSA_FN_IMM8(bmzi_b, pwd->b[i],
MSA_FN_IMM8(bseli_b, pwd->b[i],
BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
+#undef BIT_SELECT
+#undef BIT_MOVE_IF_ZERO
+#undef BIT_MOVE_IF_NOT_ZERO
#undef MSA_FN_IMM8
#define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03))
@@ -980,30 +1019,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_move_v(pwd, pwx);
}
-#define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \
-void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
- uint32_t wt) \
-{ \
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
- wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
- wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \
- uint32_t i; \
- for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \
- DEST = OPERATION; \
- } \
-}
-
-MSA_FN_VECTOR(bmnz_v, pwd->d[i],
- BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
-MSA_FN_VECTOR(bmz_v, pwd->d[i],
- BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
-MSA_FN_VECTOR(bsel_v, pwd->d[i],
- BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE))
-#undef BIT_MOVE_IF_NOT_ZERO
-#undef BIT_MOVE_IF_ZERO
-#undef BIT_SELECT
-#undef MSA_FN_VECTOR
-
void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
{
wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 11/11] target/mips: msa: Split helpers for B<CLR|NEG|SEL>.<B|H|W|D>
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (9 preceding siblings ...)
2019-09-24 13:26 ` [PATCH 10/11] target/mips: msa: Unroll loops and demacro <BMNZ|BMZ|BSEL>.V Aleksandar Markovic
@ 2019-09-24 13:26 ` Aleksandar Markovic
10 siblings, 0 replies; 13+ messages in thread
From: Aleksandar Markovic @ 2019-09-24 13:26 UTC (permalink / raw)
To: qemu-devel; +Cc: arikalo
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 18 +++-
target/mips/msa_helper.c | 227 ++++++++++++++++++++++++++++++++++++++++++-----
target/mips/translate.c | 57 ++++++++++--
3 files changed, 267 insertions(+), 35 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 27544a1..1411e0e 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -807,6 +807,21 @@ DEF_HELPER_4(msa_bmnz_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bmz_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bsel_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bclr_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bneg_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bneg_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_bset_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32)
@@ -846,9 +861,6 @@ DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bclr_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bset_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_bneg_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index eda675a..9e4f275 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -523,7 +523,210 @@ void helper_msa_bsel_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Bit Set group helpers here */
+static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int32_t b_arg2 = BIT_POSITION(arg2, df);
+ return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
+}
+
+void helper_msa_bclr_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[1]);
+ pwd->b[2] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[2]);
+ pwd->b[3] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[3]);
+ pwd->b[4] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[4]);
+ pwd->b[5] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[5]);
+ pwd->b[6] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[6]);
+ pwd->b[7] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[7]);
+ pwd->b[8] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[8]);
+ pwd->b[9] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[9]);
+ pwd->b[10] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[10]);
+ pwd->b[11] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[11]);
+ pwd->b[12] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[12]);
+ pwd->b[13] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[13]);
+ pwd->b[14] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[14]);
+ pwd->b[15] = msa_bclr_df(DF_BYTE, pws->b[0], pwt->b[15]);
+}
+
+void helper_msa_bclr_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[1]);
+ pwd->h[2] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[2]);
+ pwd->h[3] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[3]);
+ pwd->h[4] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[4]);
+ pwd->h[5] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[5]);
+ pwd->h[6] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[6]);
+ pwd->h[7] = msa_bclr_df(DF_HALF, pws->h[0], pwt->h[7]);
+}
+
+void helper_msa_bclr_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_bclr_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_bclr_df(DF_WORD, pws->w[0], pwt->w[1]);
+ pwd->w[2] = msa_bclr_df(DF_WORD, pws->w[0], pwt->w[2]);
+ pwd->w[3] = msa_bclr_df(DF_WORD, pws->w[0], pwt->w[3]);
+}
+
+void helper_msa_bclr_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_bclr_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_bclr_df(DF_DOUBLE, pws->d[0], pwt->d[1]);
+}
+
+static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int32_t b_arg2 = BIT_POSITION(arg2, df);
+ return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
+}
+
+void helper_msa_bneg_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[1]);
+ pwd->b[2] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[2]);
+ pwd->b[3] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[3]);
+ pwd->b[4] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[4]);
+ pwd->b[5] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[5]);
+ pwd->b[6] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[6]);
+ pwd->b[7] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[7]);
+ pwd->b[8] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[8]);
+ pwd->b[9] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[9]);
+ pwd->b[10] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[10]);
+ pwd->b[11] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[11]);
+ pwd->b[12] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[12]);
+ pwd->b[13] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[13]);
+ pwd->b[14] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[14]);
+ pwd->b[15] = msa_bneg_df(DF_BYTE, pws->b[0], pwt->b[15]);
+}
+
+void helper_msa_bneg_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[1]);
+ pwd->h[2] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[2]);
+ pwd->h[3] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[3]);
+ pwd->h[4] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[4]);
+ pwd->h[5] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[5]);
+ pwd->h[6] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[6]);
+ pwd->h[7] = msa_bneg_df(DF_HALF, pws->h[0], pwt->h[7]);
+}
+
+void helper_msa_bneg_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_bneg_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_bneg_df(DF_WORD, pws->w[0], pwt->w[1]);
+ pwd->w[2] = msa_bneg_df(DF_WORD, pws->w[0], pwt->w[2]);
+ pwd->w[3] = msa_bneg_df(DF_WORD, pws->w[0], pwt->w[3]);
+}
+
+void helper_msa_bneg_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_bneg_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_bneg_df(DF_DOUBLE, pws->d[0], pwt->d[1]);
+}
+
+static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
+ int64_t arg2)
+{
+ int32_t b_arg2 = BIT_POSITION(arg2, df);
+ return UNSIGNED(arg1 | (1LL << b_arg2), df);
+}
+
+void helper_msa_bset_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[1]);
+ pwd->b[2] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[2]);
+ pwd->b[3] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[3]);
+ pwd->b[4] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[4]);
+ pwd->b[5] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[5]);
+ pwd->b[6] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[6]);
+ pwd->b[7] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[7]);
+ pwd->b[8] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[8]);
+ pwd->b[9] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[9]);
+ pwd->b[10] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[10]);
+ pwd->b[11] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[11]);
+ pwd->b[12] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[12]);
+ pwd->b[13] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[13]);
+ pwd->b[14] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[14]);
+ pwd->b[15] = msa_bset_df(DF_BYTE, pws->b[0], pwt->b[15]);
+}
+
+void helper_msa_bset_h(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[1]);
+ pwd->h[2] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[2]);
+ pwd->h[3] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[3]);
+ pwd->h[4] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[4]);
+ pwd->h[5] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[5]);
+ pwd->h[6] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[6]);
+ pwd->h[7] = msa_bset_df(DF_HALF, pws->h[0], pwt->h[7]);
+}
+
+void helper_msa_bset_w(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_bset_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_bset_df(DF_WORD, pws->w[0], pwt->w[1]);
+ pwd->w[2] = msa_bset_df(DF_WORD, pws->w[0], pwt->w[2]);
+ pwd->w[3] = msa_bset_df(DF_WORD, pws->w[0], pwt->w[3]);
+}
+
+void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_bset_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_bset_df(DF_DOUBLE, pws->d[0], pwt->d[1]);
+}
/*
@@ -1220,25 +1423,6 @@ static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
return u_arg1 >> b_arg2;
}
-static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int32_t b_arg2 = BIT_POSITION(arg2, df);
- return UNSIGNED(arg1 & (~(1LL << b_arg2)), df);
-}
-
-static inline int64_t msa_bset_df(uint32_t df, int64_t arg1,
- int64_t arg2)
-{
- int32_t b_arg2 = BIT_POSITION(arg2, df);
- return UNSIGNED(arg1 | (1LL << b_arg2), df);
-}
-
-static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int32_t b_arg2 = BIT_POSITION(arg2, df);
- return UNSIGNED(arg1 ^ (1LL << b_arg2), df);
-}
-
static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
{
return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) :
@@ -1734,9 +1918,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
MSA_BINOP_DF(sll)
MSA_BINOP_DF(sra)
MSA_BINOP_DF(srl)
-MSA_BINOP_DF(bclr)
-MSA_BINOP_DF(bset)
-MSA_BINOP_DF(bneg)
MSA_BINOP_DF(addv)
MSA_BINOP_DF(subv)
MSA_BINOP_DF(max_s)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 6080c72..1a87f79 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28418,6 +28418,54 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_BCLR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_bclr_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_bclr_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_bclr_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_bclr_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_BNEG_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_bneg_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_bneg_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_bneg_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_bneg_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_BSET_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_bset_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_bset_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_bset_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_bset_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_SLL_df:
gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28487,9 +28535,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SRLR_df:
gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_BCLR_df:
- gen_helper_msa_bclr_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_MAX_U_df:
gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28505,9 +28550,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_PCKOD_df:
gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_BSET_df:
- gen_helper_msa_bset_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_MIN_S_df:
gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28526,9 +28568,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_ILVL_df:
gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_BNEG_df:
- gen_helper_msa_bneg_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_MIN_U_df:
gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread