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Fri, 18 Oct 2019 02:08:12 -0700 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iLOF2-0003T3-0g; Fri, 18 Oct 2019 02:08:12 -0700 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id A6BC713C1372; Fri, 18 Oct 2019 14:39:11 +0530 (IST) From: Sai Pavan Boddu To: Alistair Francis Subject: [PATCH v3] ssi: xilinx_spips: Skip spi bus update for few register writes Date: Fri, 18 Oct 2019 14:39:04 +0530 Message-Id: <1571389744-11740-1-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(4636009)(136003)(39860400002)(376002)(396003)(346002)(189003)(199004)(54906003)(16586007)(42186006)(2906002)(70586007)(316002)(14444005)(47776003)(305945005)(486006)(476003)(5660300002)(106002)(15650500001)(2616005)(50466002)(126002)(26005)(81166006)(6916009)(81156014)(50226002)(8676002)(336012)(6666004)(478600001)(8936002)(36756003)(103686004)(4326008)(48376002)(356004)(426003)(6266002)(70206006)(51416003)(186003); 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Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB5483 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.70.64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, Peter Maydell , qemu-devel@nongnu.org, Francisco Iglesias Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Few of the register writes need not update the spi bus state, so just return after reg write. Added few more dummy register offsets which need the same behaviour. Signed-off-by: Sai Pavan Boddu --- Changes for V2: Just skip update of spips cs and fifos Update commit message accordingly Changes for V3: Avoid checking for zynqmp qspi Skip spi bus update for few of the registers hw/ssi/xilinx_spips.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a309c71..c23de47 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -109,6 +109,7 @@ #define R_GPIO (0x30 / 4) #define R_LPBK_DLY_ADJ (0x38 / 4) #define R_LPBK_DLY_ADJ_RESET (0x33) +#define R_IOU_TAPDLY_BYPASS (0x3C / 4) #define R_TXD1 (0x80 / 4) #define R_TXD2 (0x84 / 4) #define R_TXD3 (0x88 / 4) @@ -139,6 +140,8 @@ #define R_LQSPI_STS (0xA4 / 4) #define LQSPI_STS_WR_RECVD (1 << 1) +#define R_DUMMY_CYCLE_EN (0xC8 / 4) +#define R_ECO (0xF8 / 4) #define R_MOD_ID (0xFC / 4) #define R_GQSPI_SELECT (0x144 / 4) @@ -1022,6 +1025,15 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, } s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask); no_reg_update: + /* Skip SPI bus update for below registers writes */ + switch (addr) { + case R_GPIO: + case R_LPBK_DLY_ADJ: + case R_IOU_TAPDLY_BYPASS: + case R_DUMMY_CYCLE_EN: + case R_ECO: + return; + } xilinx_spips_update_cs_lines(s); xilinx_spips_check_flush(s); xilinx_spips_update_cs_lines(s); -- 2.7.4