From: Cathy Zhang <cathy.zhang@intel.com>
To: qemu-devel@nongnu.org
Cc: Cathy Zhang <cathy.zhang@intel.com>,
pbonzini@redhat.com, ehabkost@redhat.com, rth@twiddle.net
Subject: [Resend PATCH 1/3] i386: Add MSR feature bit for MDS-NO
Date: Tue, 22 Oct 2019 15:35:26 +0800 [thread overview]
Message-ID: <1571729728-23284-2-git-send-email-cathy.zhang@intel.com> (raw)
In-Reply-To: <1571729728-23284-1-git-send-email-cathy.zhang@intel.com>
Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow
CPU models to report the feature when host supports it.
Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Tao Xu <tao3.xu@intel.com>
---
target/i386/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index eaa5395..e757149 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -777,6 +777,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define MSR_ARCH_CAP_RSBA (1U << 2)
#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
#define MSR_ARCH_CAP_SSB_NO (1U << 4)
+#define MSR_ARCH_CAP_MDS_NO (1U << 5)
#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
--
1.8.3.1
next prev parent reply other threads:[~2019-10-22 7:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-22 7:35 [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang
2019-10-22 7:35 ` Cathy Zhang [this message]
2019-10-22 7:35 ` [Resend PATCH 2/3] i386: Add macro for stibp Cathy Zhang
2019-10-22 7:35 ` [Resend PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang
2019-10-24 16:58 ` Bruce Rogers
2019-10-24 2:52 ` [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Eduardo Habkost
2019-11-11 17:31 ` Bruce Rogers
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