* [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake
@ 2019-10-22 7:35 Cathy Zhang
2019-10-22 7:35 ` [Resend PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Cathy Zhang @ 2019-10-22 7:35 UTC (permalink / raw)
To: qemu-devel; +Cc: Cathy Zhang, pbonzini, ehabkost, rth
This patchset is to add CPU model for intel processor Cooper Lake. It
will inherit features from the existing CPU model Cascadelake-Server,
meanwhile, add the platform associated new instruction and feature
for speculative execution which the host supports. There are associated
feature bit and macro defined here as needed.
Cathy Zhang (3):
i386: Add MSR feature bit for MDS-NO
i386: Add macro for stibp
i386: Add new CPU model Cooperlake
target/i386/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
target/i386/cpu.h | 3 +++
2 files changed, 63 insertions(+)
--
1.8.3.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [Resend PATCH 1/3] i386: Add MSR feature bit for MDS-NO 2019-10-22 7:35 [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang @ 2019-10-22 7:35 ` Cathy Zhang 2019-10-22 7:35 ` [Resend PATCH 2/3] i386: Add macro for stibp Cathy Zhang ` (2 subsequent siblings) 3 siblings, 0 replies; 7+ messages in thread From: Cathy Zhang @ 2019-10-22 7:35 UTC (permalink / raw) To: qemu-devel; +Cc: Cathy Zhang, pbonzini, ehabkost, rth Define MSR_ARCH_CAP_MDS_NO in the IA32_ARCH_CAPABILITIES MSR to allow CPU models to report the feature when host supports it. Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Tao Xu <tao3.xu@intel.com> --- target/i386/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index eaa5395..e757149 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -777,6 +777,7 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define MSR_ARCH_CAP_RSBA (1U << 2) #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3) #define MSR_ARCH_CAP_SSB_NO (1U << 4) +#define MSR_ARCH_CAP_MDS_NO (1U << 5) #define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5) -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Resend PATCH 2/3] i386: Add macro for stibp 2019-10-22 7:35 [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang 2019-10-22 7:35 ` [Resend PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang @ 2019-10-22 7:35 ` Cathy Zhang 2019-10-22 7:35 ` [Resend PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang 2019-10-24 2:52 ` [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Eduardo Habkost 3 siblings, 0 replies; 7+ messages in thread From: Cathy Zhang @ 2019-10-22 7:35 UTC (permalink / raw) To: qemu-devel; +Cc: Cathy Zhang, pbonzini, ehabkost, rth stibp feature is already added through the following commit. https://github.com/qemu/qemu/commit/0e8916582991b9fd0b94850a8444b8b80d0a0955 Add a macro for it to allow CPU models to report it when host supports. Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Tao Xu <tao3.xu@intel.com> --- target/i386/cpu.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e757149..8f8efd7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -717,6 +717,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +/* Single Thread Indirect Branch Predictors */ +#define CPUID_7_0_EDX_STIBP (1U << 27) #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29) /*Arch Capabilities*/ #define CPUID_7_0_EDX_CORE_CAPABILITY (1U << 30) /*Core Capability*/ #define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [Resend PATCH 3/3] i386: Add new CPU model Cooperlake 2019-10-22 7:35 [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang 2019-10-22 7:35 ` [Resend PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang 2019-10-22 7:35 ` [Resend PATCH 2/3] i386: Add macro for stibp Cathy Zhang @ 2019-10-22 7:35 ` Cathy Zhang 2019-10-24 16:58 ` Bruce Rogers 2019-10-24 2:52 ` [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Eduardo Habkost 3 siblings, 1 reply; 7+ messages in thread From: Cathy Zhang @ 2019-10-22 7:35 UTC (permalink / raw) To: qemu-devel; +Cc: Cathy Zhang, pbonzini, ehabkost, rth Cooper Lake is intel's successor to Cascade Lake, the new CPU model inherits features from Cascadelake-Server, while add one platform associated new feature: AVX512_BF16. Meanwhile, add STIBP for speculative execution. Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Tao Xu <tao3.xu@intel.com> --- target/i386/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 44f1bbd..630a190 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2612,6 +2612,66 @@ static X86CPUDefinition builtin_x86_defs[] = { } }, { + .name = "Cooperlake", + .level = 0xd, + .vendor = CPUID_VENDOR_INTEL, + .family = 6, + .model = 85, + .stepping = 10, + .features[FEAT_1_EDX] = + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | + CPUID_DE | CPUID_FP87, + .features[FEAT_1_ECX] = + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, + .features[FEAT_8000_0001_EDX] = + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, + .features[FEAT_8000_0001_ECX] = + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_7_0_EBX] = + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, + .features[FEAT_7_0_ECX] = + CPUID_7_0_ECX_PKU | + CPUID_7_0_ECX_AVX512VNNI, + .features[FEAT_7_0_EDX] = + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | + CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES, + .features[FEAT_ARCH_CAPABILITIES] = + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO, + .features[FEAT_7_1_EAX] = + CPUID_7_1_EAX_AVX512_BF16, + /* + * Missing: XSAVES (not supported by some Linux versions, + * including v4.1 to v4.12). + * KVM doesn't yet expose any XSAVES state save component, + * and the only one defined in Skylake (processor tracing) + * probably will block migration anyway. + */ + .features[FEAT_XSAVE] = + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1, + .features[FEAT_6_EAX] = + CPUID_6_EAX_ARAT, + .xlevel = 0x80000008, + .model_id = "Intel Xeon Processor (Cooperlake)", + }, + { .name = "Icelake-Client", .level = 0xd, .vendor = CPUID_VENDOR_INTEL, -- 1.8.3.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Resend PATCH 3/3] i386: Add new CPU model Cooperlake 2019-10-22 7:35 ` [Resend PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang @ 2019-10-24 16:58 ` Bruce Rogers 0 siblings, 0 replies; 7+ messages in thread From: Bruce Rogers @ 2019-10-24 16:58 UTC (permalink / raw) To: qemu-devel@nongnu.org, cathy.zhang@intel.com Cc: pbonzini@redhat.com, ehabkost@redhat.com, rth@twiddle.net On Tue, 2019-10-22 at 15:35 +0800, Cathy Zhang wrote: > Cooper Lake is intel's successor to Cascade Lake, the new > CPU model inherits features from Cascadelake-Server, while > add one platform associated new feature: AVX512_BF16. Meanwhile, > add STIBP for speculative execution. > > Signed-off-by: Cathy Zhang <cathy.zhang@intel.com> > Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> > Reviewed-by: Tao Xu <tao3.xu@intel.com> > --- > target/i386/cpu.c | 60 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 60 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 44f1bbd..630a190 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -2612,6 +2612,66 @@ static X86CPUDefinition builtin_x86_defs[] = { > } > }, > { > + .name = "Cooperlake", > + .level = 0xd, > + .vendor = CPUID_VENDOR_INTEL, > + .family = 6, > + .model = 85, > + .stepping = 10, > + .features[FEAT_1_EDX] = > + CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | > CPUID_MMX | > + CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | > CPUID_MCA | > + CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | > CPUID_CX8 | > + CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | > CPUID_PSE | > + CPUID_DE | CPUID_FP87, > + .features[FEAT_1_ECX] = > + CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES | > + CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | > + CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | > + CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | > + CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | > CPUID_EXT_MOVBE | > + CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND, > + .features[FEAT_8000_0001_EDX] = > + CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP | > + CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, > + .features[FEAT_8000_0001_ECX] = > + CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | > CPUID_EXT3_3DNOWPREFETCH, > + .features[FEAT_7_0_EBX] = > + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | > + CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | > CPUID_7_0_EBX_SMEP | > + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | > CPUID_7_0_EBX_INVPCID | > + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | > CPUID_7_0_EBX_ADX | > + CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB | > + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | > + CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD | > + CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT, > + .features[FEAT_7_0_ECX] = > + CPUID_7_0_ECX_PKU | > + CPUID_7_0_ECX_AVX512VNNI, > + .features[FEAT_7_0_EDX] = > + CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP | > + CPUID_7_0_EDX_SPEC_CTRL_SSBD | > CPUID_7_0_EDX_ARCH_CAPABILITIES, > + .features[FEAT_ARCH_CAPABILITIES] = > + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | > + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO, > + .features[FEAT_7_1_EAX] = > + CPUID_7_1_EAX_AVX512_BF16, > + /* > + * Missing: XSAVES (not supported by some Linux versions, > + * including v4.1 to v4.12). > + * KVM doesn't yet expose any XSAVES state save component, > + * and the only one defined in Skylake (processor tracing) > + * probably will block migration anyway. > + */ > + .features[FEAT_XSAVE] = > + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | > + CPUID_XSAVE_XGETBV1, > + .features[FEAT_6_EAX] = > + CPUID_6_EAX_ARAT, > + .xlevel = 0x80000008, > + .model_id = "Intel Xeon Processor (Cooperlake)", > + }, > + { > .name = "Icelake-Client", > .level = 0xd, > .vendor = CPUID_VENDOR_INTEL, Looks fine to me. Reviewed-by: Bruce Rogers <brogers@suse.com> - Bruce ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake 2019-10-22 7:35 [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang ` (2 preceding siblings ...) 2019-10-22 7:35 ` [Resend PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang @ 2019-10-24 2:52 ` Eduardo Habkost 2019-11-11 17:31 ` Bruce Rogers 3 siblings, 1 reply; 7+ messages in thread From: Eduardo Habkost @ 2019-10-24 2:52 UTC (permalink / raw) To: Cathy Zhang; +Cc: pbonzini, qemu-devel, rth On Tue, Oct 22, 2019 at 03:35:25PM +0800, Cathy Zhang wrote: > This patchset is to add CPU model for intel processor Cooper Lake. It > will inherit features from the existing CPU model Cascadelake-Server, > meanwhile, add the platform associated new instruction and feature > for speculative execution which the host supports. There are associated > feature bit and macro defined here as needed. Queued, thanks. > > Cathy Zhang (3): > i386: Add MSR feature bit for MDS-NO > i386: Add macro for stibp > i386: Add new CPU model Cooperlake > > target/i386/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > target/i386/cpu.h | 3 +++ > 2 files changed, 63 insertions(+) > > -- > 1.8.3.1 > -- Eduardo ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake 2019-10-24 2:52 ` [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Eduardo Habkost @ 2019-11-11 17:31 ` Bruce Rogers 0 siblings, 0 replies; 7+ messages in thread From: Bruce Rogers @ 2019-11-11 17:31 UTC (permalink / raw) To: ehabkost@redhat.com, cathy.zhang@intel.com Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, rth@twiddle.net On Wed, 2019-10-23 at 23:52 -0300, Eduardo Habkost wrote: > On Tue, Oct 22, 2019 at 03:35:25PM +0800, Cathy Zhang wrote: > > This patchset is to add CPU model for intel processor Cooper Lake. > > It > > will inherit features from the existing CPU model Cascadelake- > > Server, > > meanwhile, add the platform associated new instruction and feature > > for speculative execution which the host supports. There are > > associated > > feature bit and macro defined here as needed. > > Queued, thanks. > > > Cathy Zhang (3): > > i386: Add MSR feature bit for MDS-NO > > i386: Add macro for stibp > > i386: Add new CPU model Cooperlake > > > > target/i386/cpu.c | 60 > > +++++++++++++++++++++++++++++++++++++++++++++++++++++++ > > target/i386/cpu.h | 3 +++ > > 2 files changed, 63 insertions(+) > > Hi Eduardo, Is this going to make it into v4.2? Regards, Bruce ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-11-11 17:35 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-10-22 7:35 [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Cathy Zhang 2019-10-22 7:35 ` [Resend PATCH 1/3] i386: Add MSR feature bit for MDS-NO Cathy Zhang 2019-10-22 7:35 ` [Resend PATCH 2/3] i386: Add macro for stibp Cathy Zhang 2019-10-22 7:35 ` [Resend PATCH 3/3] i386: Add new CPU model Cooperlake Cathy Zhang 2019-10-24 16:58 ` Bruce Rogers 2019-10-24 2:52 ` [Resend PATCH 0/3] Add CPU model for intel processor Cooper Lake Eduardo Habkost 2019-11-11 17:31 ` Bruce Rogers
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