* [PULL 00/23] Net patches
@ 2020-03-02 7:39 Jason Wang
2020-03-02 7:39 ` [PULL 01/23] dp8393x: Mask EOL bit from descriptor addresses Jason Wang
2020-03-02 7:39 ` [PULL 02/23] dp8393x: Always use 32-bit accesses Jason Wang
0 siblings, 2 replies; 4+ messages in thread
From: Jason Wang @ 2020-03-02 7:39 UTC (permalink / raw)
To: peter.maydell; +Cc: Jason Wang, qemu-devel
The following changes since commit e0175b71638cf4398903c0d25f93fe62e0606389:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200228' into staging (2020-02-28 16:39:27 +0000)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
for you to fetch changes up to 41aa2e3f9b27fd259a13711545d933a20f1d2f16:
l2tpv3: fix RFC number typo in qemu-options.hx (2020-03-02 15:30:08 +0800)
----------------------------------------------------------------
----------------------------------------------------------------
Bin Meng (1):
hw: net: cadence_gem: Fix build errors in DB_PRINT()
Finn Thain (14):
dp8393x: Mask EOL bit from descriptor addresses
dp8393x: Always use 32-bit accesses
dp8393x: Clean up endianness hacks
dp8393x: Have dp8393x_receive() return the packet size
dp8393x: Update LLFA and CRDA registers from rx descriptor
dp8393x: Clear RRRA command register bit only when appropriate
dp8393x: Implement packet size limit and RBAE interrupt
dp8393x: Don't clobber packet checksum
dp8393x: Use long-word-aligned RRA pointers in 32-bit mode
dp8393x: Pad frames to word or long word boundary
dp8393x: Clear descriptor in_use field to release packet
dp8393x: Always update RRA pointers and sequence numbers
dp8393x: Don't reset Silicon Revision register
dp8393x: Don't stop reception upon RBE interrupt assertion
Lukas Straub (4):
block/replication.c: Ignore requests after failover
tests/test-replication.c: Add test for for secondary node continuing replication
net/filter.c: Add Options to insert filters anywhere in the filter list
colo: Update Documentation for continuous replication
Stefan Hajnoczi (1):
l2tpv3: fix RFC number typo in qemu-options.hx
Yuri Benditovich (3):
e1000e: Avoid hw_error if legacy mode used
NetRxPkt: Introduce support for additional hash types
NetRxPkt: fix hash calculation of IPV6 TCP
block/replication.c | 35 ++++++-
docs/COLO-FT.txt | 224 +++++++++++++++++++++++++++++++++------------
docs/block-replication.txt | 28 ++++--
hw/net/cadence_gem.c | 11 ++-
hw/net/dp8393x.c | 200 ++++++++++++++++++++++++++--------------
hw/net/e1000e_core.c | 15 +--
hw/net/net_rx_pkt.c | 44 ++++++++-
hw/net/net_rx_pkt.h | 6 +-
hw/net/trace-events | 4 +
include/net/filter.h | 2 +
net/filter.c | 92 ++++++++++++++++++-
qemu-options.hx | 35 +++++--
tests/test-replication.c | 52 +++++++++++
13 files changed, 591 insertions(+), 157 deletions(-)
^ permalink raw reply [flat|nested] 4+ messages in thread* [PULL 01/23] dp8393x: Mask EOL bit from descriptor addresses 2020-03-02 7:39 [PULL 00/23] Net patches Jason Wang @ 2020-03-02 7:39 ` Jason Wang 2020-03-02 7:39 ` [PULL 02/23] dp8393x: Always use 32-bit accesses Jason Wang 1 sibling, 0 replies; 4+ messages in thread From: Jason Wang @ 2020-03-02 7:39 UTC (permalink / raw) To: peter.maydell; +Cc: qemu-devel, Finn Thain From: Finn Thain <fthain@telegraphics.com.au> The Least Significant bit of a descriptor address register is used as an EOL flag. It has to be masked when the register value is to be used as an actual address for copying memory around. But when the registers are to be updated the EOL bit should not be masked. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Tested-by: Laurent Vivier <laurent@vivier.eu> --- hw/net/dp8393x.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 7045193..216d44b 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -145,6 +145,9 @@ do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0) #define SONIC_ISR_PINT 0x0800 #define SONIC_ISR_LCD 0x1000 +#define SONIC_DESC_EOL 0x0001 +#define SONIC_DESC_ADDR 0xFFFE + #define TYPE_DP8393X "dp8393x" #define DP8393X(obj) OBJECT_CHECK(dp8393xState, (obj), TYPE_DP8393X) @@ -197,7 +200,8 @@ static uint32_t dp8393x_crba(dp8393xState *s) static uint32_t dp8393x_crda(dp8393xState *s) { - return (s->regs[SONIC_URDA] << 16) | s->regs[SONIC_CRDA]; + return (s->regs[SONIC_URDA] << 16) | + (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR); } static uint32_t dp8393x_rbwc(dp8393xState *s) @@ -217,7 +221,8 @@ static uint32_t dp8393x_tsa(dp8393xState *s) static uint32_t dp8393x_ttda(dp8393xState *s) { - return (s->regs[SONIC_UTDA] << 16) | s->regs[SONIC_TTDA]; + return (s->regs[SONIC_UTDA] << 16) | + (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR); } static uint32_t dp8393x_wt(dp8393xState *s) @@ -509,7 +514,7 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) MEMTXATTRS_UNSPECIFIED, s->data, size); s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; - if (dp8393x_get(s, width, 0) & 0x1) { + if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) { /* EOL detected */ break; } @@ -765,13 +770,13 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, /* XXX: Check byte ordering */ /* Check for EOL */ - if (s->regs[SONIC_LLFA] & 0x1) { + if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { /* Are we still in resource exhaustion? */ size = sizeof(uint16_t) * 1 * width; address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, s->data, size); - if (dp8393x_get(s, width, 0) & 0x1) { + if (dp8393x_get(s, width, 0) & SONIC_DESC_EOL) { /* Still EOL ; stop reception */ return -1; } else { @@ -831,7 +836,7 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, MEMTXATTRS_UNSPECIFIED, s->data, size); s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); - if (s->regs[SONIC_LLFA] & 0x1) { + if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) { /* EOL detected */ s->regs[SONIC_ISR] |= SONIC_ISR_RDE; } else { -- 2.5.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PULL 02/23] dp8393x: Always use 32-bit accesses 2020-03-02 7:39 [PULL 00/23] Net patches Jason Wang 2020-03-02 7:39 ` [PULL 01/23] dp8393x: Mask EOL bit from descriptor addresses Jason Wang @ 2020-03-02 7:39 ` Jason Wang 1 sibling, 0 replies; 4+ messages in thread From: Jason Wang @ 2020-03-02 7:39 UTC (permalink / raw) To: peter.maydell; +Cc: Jason Wang, qemu-devel, Finn Thain From: Finn Thain <fthain@telegraphics.com.au> The DP83932 and DP83934 have 32 data lines. The datasheet says, Data Bus: These bidirectional lines are used to transfer data on the system bus. When the SONIC is a bus master, 16-bit data is transferred on D15-D0 and 32-bit data is transferred on D31-D0. When the SONIC is accessed as a slave, register data is driven onto lines D15-D0. D31-D16 are held TRI-STATE if SONIC is in 16-bit mode. If SONIC is in 32-bit mode, they are driven, but invalid. Always use 32-bit accesses both as bus master and bus slave. Force the MSW to zero in bus master mode. This gets the Linux 'jazzsonic' driver working, and avoids the need for prior hacks to make the NetBSD 'sn' driver work. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Tested-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Jason Wang <jasowang@redhat.com> --- hw/net/dp8393x.c | 47 +++++++++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 216d44b..51b71da 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -246,9 +246,19 @@ static void dp8393x_put(dp8393xState *s, int width, int offset, uint16_t val) { if (s->big_endian) { - s->data[offset * width + width - 1] = cpu_to_be16(val); + if (width == 2) { + s->data[offset * 2] = 0; + s->data[offset * 2 + 1] = cpu_to_be16(val); + } else { + s->data[offset] = cpu_to_be16(val); + } } else { - s->data[offset * width] = cpu_to_le16(val); + if (width == 2) { + s->data[offset * 2] = cpu_to_le16(val); + s->data[offset * 2 + 1] = 0; + } else { + s->data[offset] = cpu_to_le16(val); + } } } @@ -590,7 +600,7 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); - return val; + return s->big_endian ? val << 16 : val; } static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, @@ -598,13 +608,14 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, { dp8393xState *s = opaque; int reg = addr >> s->it_shift; + uint32_t val = s->big_endian ? data >> 16 : data; - DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]); + DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); switch (reg) { /* Command register */ case SONIC_CR: - dp8393x_do_command(s, data); + dp8393x_do_command(s, val); break; /* Prevent write to read-only registers */ case SONIC_CAP2: @@ -617,36 +628,36 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, /* Accept write to some registers only when in reset mode */ case SONIC_DCR: if (s->regs[SONIC_CR] & SONIC_CR_RST) { - s->regs[reg] = data & 0xbfff; + s->regs[reg] = val & 0xbfff; } else { DPRINTF("writing to DCR invalid\n"); } break; case SONIC_DCR2: if (s->regs[SONIC_CR] & SONIC_CR_RST) { - s->regs[reg] = data & 0xf017; + s->regs[reg] = val & 0xf017; } else { DPRINTF("writing to DCR2 invalid\n"); } break; /* 12 lower bytes are Read Only */ case SONIC_TCR: - s->regs[reg] = data & 0xf000; + s->regs[reg] = val & 0xf000; break; /* 9 lower bytes are Read Only */ case SONIC_RCR: - s->regs[reg] = data & 0xffe0; + s->regs[reg] = val & 0xffe0; break; /* Ignore most significant bit */ case SONIC_IMR: - s->regs[reg] = data & 0x7fff; + s->regs[reg] = val & 0x7fff; dp8393x_update_irq(s); break; /* Clear bits by writing 1 to them */ case SONIC_ISR: - data &= s->regs[reg]; - s->regs[reg] &= ~data; - if (data & SONIC_ISR_RBE) { + val &= s->regs[reg]; + s->regs[reg] &= ~val; + if (val & SONIC_ISR_RBE) { dp8393x_do_read_rra(s); } dp8393x_update_irq(s); @@ -659,17 +670,17 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, case SONIC_REA: case SONIC_RRP: case SONIC_RWP: - s->regs[reg] = data & 0xfffe; + s->regs[reg] = val & 0xfffe; break; /* Invert written value for some registers */ case SONIC_CRCT: case SONIC_FAET: case SONIC_MPT: - s->regs[reg] = data ^ 0xffff; + s->regs[reg] = val ^ 0xffff; break; /* All other registers have no special contrainst */ default: - s->regs[reg] = data; + s->regs[reg] = val; } if (reg == SONIC_WT0 || reg == SONIC_WT1) { @@ -680,8 +691,8 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, static const MemoryRegionOps dp8393x_ops = { .read = dp8393x_read, .write = dp8393x_write, - .impl.min_access_size = 2, - .impl.max_access_size = 2, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .endianness = DEVICE_NATIVE_ENDIAN, }; -- 2.5.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PULL 00/23] Net patches
@ 2020-03-02 7:40 Jason Wang
2020-03-02 7:40 ` [PULL 02/23] dp8393x: Always use 32-bit accesses Jason Wang
0 siblings, 1 reply; 4+ messages in thread
From: Jason Wang @ 2020-03-02 7:40 UTC (permalink / raw)
To: peter.maydell; +Cc: Jason Wang, qemu-devel
The following changes since commit e0175b71638cf4398903c0d25f93fe62e0606389:
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200228' into staging (2020-02-28 16:39:27 +0000)
are available in the git repository at:
https://github.com/jasowang/qemu.git tags/net-pull-request
for you to fetch changes up to 41aa2e3f9b27fd259a13711545d933a20f1d2f16:
l2tpv3: fix RFC number typo in qemu-options.hx (2020-03-02 15:30:08 +0800)
----------------------------------------------------------------
----------------------------------------------------------------
Bin Meng (1):
hw: net: cadence_gem: Fix build errors in DB_PRINT()
Finn Thain (14):
dp8393x: Mask EOL bit from descriptor addresses
dp8393x: Always use 32-bit accesses
dp8393x: Clean up endianness hacks
dp8393x: Have dp8393x_receive() return the packet size
dp8393x: Update LLFA and CRDA registers from rx descriptor
dp8393x: Clear RRRA command register bit only when appropriate
dp8393x: Implement packet size limit and RBAE interrupt
dp8393x: Don't clobber packet checksum
dp8393x: Use long-word-aligned RRA pointers in 32-bit mode
dp8393x: Pad frames to word or long word boundary
dp8393x: Clear descriptor in_use field to release packet
dp8393x: Always update RRA pointers and sequence numbers
dp8393x: Don't reset Silicon Revision register
dp8393x: Don't stop reception upon RBE interrupt assertion
Lukas Straub (4):
block/replication.c: Ignore requests after failover
tests/test-replication.c: Add test for for secondary node continuing replication
net/filter.c: Add Options to insert filters anywhere in the filter list
colo: Update Documentation for continuous replication
Stefan Hajnoczi (1):
l2tpv3: fix RFC number typo in qemu-options.hx
Yuri Benditovich (3):
e1000e: Avoid hw_error if legacy mode used
NetRxPkt: Introduce support for additional hash types
NetRxPkt: fix hash calculation of IPV6 TCP
block/replication.c | 35 ++++++-
docs/COLO-FT.txt | 224 +++++++++++++++++++++++++++++++++------------
docs/block-replication.txt | 28 ++++--
hw/net/cadence_gem.c | 11 ++-
hw/net/dp8393x.c | 200 ++++++++++++++++++++++++++--------------
hw/net/e1000e_core.c | 15 +--
hw/net/net_rx_pkt.c | 44 ++++++++-
hw/net/net_rx_pkt.h | 6 +-
hw/net/trace-events | 4 +
include/net/filter.h | 2 +
net/filter.c | 92 ++++++++++++++++++-
qemu-options.hx | 35 +++++--
tests/test-replication.c | 52 +++++++++++
13 files changed, 591 insertions(+), 157 deletions(-)
^ permalink raw reply [flat|nested] 4+ messages in thread* [PULL 02/23] dp8393x: Always use 32-bit accesses 2020-03-02 7:40 [PULL 00/23] Net patches Jason Wang @ 2020-03-02 7:40 ` Jason Wang 0 siblings, 0 replies; 4+ messages in thread From: Jason Wang @ 2020-03-02 7:40 UTC (permalink / raw) To: peter.maydell; +Cc: Jason Wang, qemu-devel, Finn Thain From: Finn Thain <fthain@telegraphics.com.au> The DP83932 and DP83934 have 32 data lines. The datasheet says, Data Bus: These bidirectional lines are used to transfer data on the system bus. When the SONIC is a bus master, 16-bit data is transferred on D15-D0 and 32-bit data is transferred on D31-D0. When the SONIC is accessed as a slave, register data is driven onto lines D15-D0. D31-D16 are held TRI-STATE if SONIC is in 16-bit mode. If SONIC is in 32-bit mode, they are driven, but invalid. Always use 32-bit accesses both as bus master and bus slave. Force the MSW to zero in bus master mode. This gets the Linux 'jazzsonic' driver working, and avoids the need for prior hacks to make the NetBSD 'sn' driver work. Signed-off-by: Finn Thain <fthain@telegraphics.com.au> Tested-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Jason Wang <jasowang@redhat.com> --- hw/net/dp8393x.c | 47 +++++++++++++++++++++++++++++------------------ 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index 216d44b..51b71da 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -246,9 +246,19 @@ static void dp8393x_put(dp8393xState *s, int width, int offset, uint16_t val) { if (s->big_endian) { - s->data[offset * width + width - 1] = cpu_to_be16(val); + if (width == 2) { + s->data[offset * 2] = 0; + s->data[offset * 2 + 1] = cpu_to_be16(val); + } else { + s->data[offset] = cpu_to_be16(val); + } } else { - s->data[offset * width] = cpu_to_le16(val); + if (width == 2) { + s->data[offset * 2] = cpu_to_le16(val); + s->data[offset * 2 + 1] = 0; + } else { + s->data[offset] = cpu_to_le16(val); + } } } @@ -590,7 +600,7 @@ static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size) DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]); - return val; + return s->big_endian ? val << 16 : val; } static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, @@ -598,13 +608,14 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, { dp8393xState *s = opaque; int reg = addr >> s->it_shift; + uint32_t val = s->big_endian ? data >> 16 : data; - DPRINTF("write 0x%04x to reg %s\n", (uint16_t)data, reg_names[reg]); + DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]); switch (reg) { /* Command register */ case SONIC_CR: - dp8393x_do_command(s, data); + dp8393x_do_command(s, val); break; /* Prevent write to read-only registers */ case SONIC_CAP2: @@ -617,36 +628,36 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, /* Accept write to some registers only when in reset mode */ case SONIC_DCR: if (s->regs[SONIC_CR] & SONIC_CR_RST) { - s->regs[reg] = data & 0xbfff; + s->regs[reg] = val & 0xbfff; } else { DPRINTF("writing to DCR invalid\n"); } break; case SONIC_DCR2: if (s->regs[SONIC_CR] & SONIC_CR_RST) { - s->regs[reg] = data & 0xf017; + s->regs[reg] = val & 0xf017; } else { DPRINTF("writing to DCR2 invalid\n"); } break; /* 12 lower bytes are Read Only */ case SONIC_TCR: - s->regs[reg] = data & 0xf000; + s->regs[reg] = val & 0xf000; break; /* 9 lower bytes are Read Only */ case SONIC_RCR: - s->regs[reg] = data & 0xffe0; + s->regs[reg] = val & 0xffe0; break; /* Ignore most significant bit */ case SONIC_IMR: - s->regs[reg] = data & 0x7fff; + s->regs[reg] = val & 0x7fff; dp8393x_update_irq(s); break; /* Clear bits by writing 1 to them */ case SONIC_ISR: - data &= s->regs[reg]; - s->regs[reg] &= ~data; - if (data & SONIC_ISR_RBE) { + val &= s->regs[reg]; + s->regs[reg] &= ~val; + if (val & SONIC_ISR_RBE) { dp8393x_do_read_rra(s); } dp8393x_update_irq(s); @@ -659,17 +670,17 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, case SONIC_REA: case SONIC_RRP: case SONIC_RWP: - s->regs[reg] = data & 0xfffe; + s->regs[reg] = val & 0xfffe; break; /* Invert written value for some registers */ case SONIC_CRCT: case SONIC_FAET: case SONIC_MPT: - s->regs[reg] = data ^ 0xffff; + s->regs[reg] = val ^ 0xffff; break; /* All other registers have no special contrainst */ default: - s->regs[reg] = data; + s->regs[reg] = val; } if (reg == SONIC_WT0 || reg == SONIC_WT1) { @@ -680,8 +691,8 @@ static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data, static const MemoryRegionOps dp8393x_ops = { .read = dp8393x_read, .write = dp8393x_write, - .impl.min_access_size = 2, - .impl.max_access_size = 2, + .impl.min_access_size = 4, + .impl.max_access_size = 4, .endianness = DEVICE_NATIVE_ENDIAN, }; -- 2.5.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-03-02 7:43 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-03-02 7:39 [PULL 00/23] Net patches Jason Wang 2020-03-02 7:39 ` [PULL 01/23] dp8393x: Mask EOL bit from descriptor addresses Jason Wang 2020-03-02 7:39 ` [PULL 02/23] dp8393x: Always use 32-bit accesses Jason Wang -- strict thread matches above, loose matches on Subject: below -- 2020-03-02 7:40 [PULL 00/23] Net patches Jason Wang 2020-03-02 7:40 ` [PULL 02/23] dp8393x: Always use 32-bit accesses Jason Wang
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