[PATCH v1 3/3] i386: Add support for save/load IA32_PEBS_DATA_CFG MSR

[Luwei Kang <luwei.kang@intel.com>]

Add support for save/load PEBS baseline feature
IA32_PEBS_DATA_CFG MSR.

Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
 target/i386/cpu.h     |  2 ++
 target/i386/kvm.c     | 14 ++++++++++++++
 target/i386/machine.c | 24 ++++++++++++++++++++++++
 3 files changed, 40 insertions(+)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 872a495..a9a7b3f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -413,6 +413,7 @@ typedef enum X86Seg {
 #define MSR_CORE_PERF_GLOBAL_OVF_CTRL   0x390
 
 #define MSR_IA32_PEBS_ENABLE            0x3f1
+#define MSR_IA32_PEBS_DATA_CFG          0x3f2
 #define MSR_IA32_DS_AREA                0x600
 
 #define MSR_MC0_CTL                     0x400
@@ -1449,6 +1450,7 @@ typedef struct CPUX86State {
 
     uint64_t msr_pebs_enable;
     uint64_t msr_ds_area;
+    uint64_t msr_pebs_data_cfg;
 
     uint64_t pat;
     uint32_t smbase;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 1043961..ab4e7bb 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -104,6 +104,7 @@ static bool has_msr_core_capabs;
 static bool has_msr_vmx_vmfunc;
 static bool has_msr_pebs_enable;
 static bool has_msr_ds_area;
+static bool has_msr_pebs_data_cfg;
 
 static uint32_t has_architectural_pmu_version;
 static uint32_t num_architectural_pmu_gp_counters;
@@ -2056,6 +2057,9 @@ static int kvm_get_supported_msrs(KVMState *s)
             case MSR_IA32_DS_AREA:
                 has_msr_ds_area = true;
                 break;
+            case MSR_IA32_PEBS_DATA_CFG:
+                has_msr_pebs_data_cfg = true;
+                break;
             }
         }
     }
@@ -2786,6 +2790,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
                 kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA,
                                   env->msr_ds_area);
             }
+            if (has_msr_pebs_data_cfg) {
+                kvm_msr_entry_add(cpu, MSR_IA32_PEBS_DATA_CFG,
+                                  env->msr_pebs_data_cfg);
+            }
         }
 
         /*
@@ -3177,6 +3185,9 @@ static int kvm_get_msrs(X86CPU *cpu)
         if (has_msr_ds_area) {
             kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0);
         }
+        if (has_msr_pebs_data_cfg) {
+            kvm_msr_entry_add(cpu, MSR_IA32_PEBS_DATA_CFG, 0);
+        }
     }
 
     if (env->mcg_cap) {
@@ -3431,6 +3442,9 @@ static int kvm_get_msrs(X86CPU *cpu)
         case MSR_IA32_DS_AREA:
             env->msr_ds_area = msrs[i].data;
             break;
+        case MSR_IA32_PEBS_DATA_CFG:
+            env->msr_pebs_data_cfg = msrs[i].data;
+            break;
         case HV_X64_MSR_HYPERCALL:
             env->msr_hv_hypercall = msrs[i].data;
             break;
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 82a2101..58b786d 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -670,6 +670,29 @@ static const VMStateDescription vmstate_msr_pebs_via_ds = {
     }
 };
 
+static bool pebs_baseline_needed(void *opaque)
+{
+    X86CPU *cpu = opaque;
+    CPUX86State *env = &cpu->env;
+
+    if (env->msr_pebs_data_cfg) {
+        return true;
+    }
+
+    return false;
+}
+
+static const VMStateDescription vmstate_msr_pebs_baseline = {
+    .name = "cpu/msr_pebs_baseline",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = pebs_baseline_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(env.msr_pebs_data_cfg, X86CPU),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static bool mpx_needed(void *opaque)
 {
     X86CPU *cpu = opaque;
@@ -1424,6 +1447,7 @@ VMStateDescription vmstate_x86_cpu = {
         &vmstate_msr_ia32_feature_control,
         &vmstate_msr_architectural_pmu,
         &vmstate_msr_pebs_via_ds,
+        &vmstate_msr_pebs_baseline,
         &vmstate_mpx,
         &vmstate_msr_hypercall_hypercall,
         &vmstate_msr_hyperv_vapic,
-- 
1.8.3.1