From: Liu Yi L <yi.l.liu@intel.com>
To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com
Cc: jean-philippe@linaro.org, kevin.tian@intel.com,
yi.l.liu@intel.com, Yi Sun <yi.y.sun@linux.intel.com>,
Eduardo Habkost <ehabkost@redhat.com>,
kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com,
eric.auger@redhat.com, yi.y.sun@intel.com,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
pbonzini@redhat.com, hao.wu@intel.com,
Richard Henderson <rth@twiddle.net>,
david@gibson.dropbear.id.au
Subject: [PATCH v2 22/22] intel_iommu: modify x-scalable-mode to be string option
Date: Sun, 29 Mar 2020 21:25:01 -0700 [thread overview]
Message-ID: <1585542301-84087-23-git-send-email-yi.l.liu@intel.com> (raw)
In-Reply-To: <1585542301-84087-1-git-send-email-yi.l.liu@intel.com>
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
related to scalable mode translation, thus there are multiple combinations.
While this vIOMMU implementation wants simplify it for user by providing
typical combinations. User could config it by "x-scalable-mode" option. The
usage is as below:
"-device intel-iommu,x-scalable-mode=["legacy"|"modern"|"off"]"
- "legacy": gives support for SL page table
- "modern": gives support for FL page table, pasid, virtual command
- "off": no scalable mode support
- if not configured, means no scalable mode support, if not proper
configured, will throw error
Note: this patch is supposed to be merged when the whole vSVA patch series
were merged.
Cc: Kevin Tian <kevin.tian@intel.com>
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Cc: Peter Xu <peterx@redhat.com>
Cc: Yi Sun <yi.y.sun@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
---
hw/i386/intel_iommu.c | 30 ++++++++++++++++++++++++++++--
hw/i386/intel_iommu_internal.h | 4 ++++
include/hw/i386/intel_iommu.h | 2 ++
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index e8877d4..2e745e8 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -4056,7 +4056,7 @@ static Property vtd_properties[] = {
DEFINE_PROP_UINT8("aw-bits", IntelIOMMUState, aw_bits,
VTD_HOST_ADDRESS_WIDTH),
DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
- DEFINE_PROP_BOOL("x-scalable-mode", IntelIOMMUState, scalable_mode, FALSE),
+ DEFINE_PROP_STRING("x-scalable-mode", IntelIOMMUState, scalable_mode_str),
DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true),
DEFINE_PROP_END_OF_LIST(),
};
@@ -4688,8 +4688,12 @@ static void vtd_init(IntelIOMMUState *s)
}
/* TODO: read cap/ecap from host to decide which cap to be exposed. */
- if (s->scalable_mode) {
+ if (s->scalable_mode && !s->scalable_modern) {
s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_SLTS;
+ } else if (s->scalable_mode && s->scalable_modern) {
+ s->ecap |= VTD_ECAP_SMTS | VTD_ECAP_SRS | VTD_ECAP_PASID
+ | VTD_ECAP_FLTS | VTD_ECAP_PSS | VTD_ECAP_VCS;
+ s->vccap |= VTD_VCCAP_PAS;
}
vtd_reset_caches(s);
@@ -4821,6 +4825,28 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
return false;
}
+ if (s->scalable_mode_str &&
+ (strcmp(s->scalable_mode_str, "off") &&
+ strcmp(s->scalable_mode_str, "modern") &&
+ strcmp(s->scalable_mode_str, "legacy"))) {
+ error_setg(errp, "Invalid x-scalable-mode config,"
+ "Please use \"modern\", \"legacy\" or \"off\"");
+ return false;
+ }
+
+ if (s->scalable_mode_str &&
+ !strcmp(s->scalable_mode_str, "legacy")) {
+ s->scalable_mode = true;
+ s->scalable_modern = false;
+ } else if (s->scalable_mode_str &&
+ !strcmp(s->scalable_mode_str, "modern")) {
+ s->scalable_mode = true;
+ s->scalable_modern = true;
+ } else {
+ s->scalable_mode = false;
+ s->scalable_modern = false;
+ }
+
return true;
}
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 4910e63..e0719bc 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -196,8 +196,12 @@
#define VTD_ECAP_PT (1ULL << 6)
#define VTD_ECAP_MHMV (15ULL << 20)
#define VTD_ECAP_SRS (1ULL << 31)
+#define VTD_ECAP_PSS (19ULL << 35)
+#define VTD_ECAP_PASID (1ULL << 40)
#define VTD_ECAP_SMTS (1ULL << 43)
+#define VTD_ECAP_VCS (1ULL << 44)
#define VTD_ECAP_SLTS (1ULL << 46)
+#define VTD_ECAP_FLTS (1ULL << 47)
/* CAP_REG */
/* (offset >> 4) << 24 */
diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h
index 626c1cd..3831ba7 100644
--- a/include/hw/i386/intel_iommu.h
+++ b/include/hw/i386/intel_iommu.h
@@ -263,6 +263,8 @@ struct IntelIOMMUState {
bool caching_mode; /* RO - is cap CM enabled? */
bool scalable_mode; /* RO - is Scalable Mode supported? */
+ char *scalable_mode_str; /* RO - admin's Scalable Mode config */
+ bool scalable_modern; /* RO - is modern SM supported? */
dma_addr_t root; /* Current root table pointer */
bool root_scalable; /* Type of root table (scalable or not) */
--
2.7.4
next prev parent reply other threads:[~2020-03-30 4:22 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-30 4:24 [PATCH v2 00/22] intel_iommu: expose Shared Virtual Addressing to VMs Liu Yi L
2020-03-30 4:24 ` [PATCH v2 01/22] scripts/update-linux-headers: Import iommu.h Liu Yi L
2020-03-30 4:24 ` [PATCH v2 02/22] header file update VFIO/IOMMU vSVA APIs Liu Yi L
2020-03-30 4:24 ` [PATCH v2 03/22] vfio: check VFIO_TYPE1_NESTING_IOMMU support Liu Yi L
2020-03-30 9:36 ` Auger Eric
2020-03-31 6:08 ` Liu, Yi L
2020-03-30 4:24 ` [PATCH v2 04/22] hw/iommu: introduce HostIOMMUContext Liu Yi L
2020-03-30 17:22 ` Auger Eric
2020-03-31 4:10 ` Liu, Yi L
2020-03-31 7:47 ` Auger Eric
2020-03-31 12:43 ` Liu, Yi L
2020-04-06 8:04 ` Liu, Yi L
2020-04-06 10:30 ` Auger Eric
2020-03-30 4:24 ` [PATCH v2 05/22] hw/pci: modify pci_setup_iommu() to set PCIIOMMUOps Liu Yi L
2020-03-30 11:02 ` Auger Eric
2020-04-02 8:52 ` Liu, Yi L
2020-04-02 12:41 ` Auger Eric
2020-04-02 13:37 ` Liu, Yi L
2020-04-02 13:49 ` Auger Eric
2020-04-06 6:27 ` Liu, Yi L
2020-04-06 10:04 ` Auger Eric
2020-03-30 4:24 ` [PATCH v2 06/22] hw/pci: introduce pci_device_set/unset_iommu_context() Liu Yi L
2020-03-30 17:30 ` Auger Eric
2020-03-31 12:14 ` Liu, Yi L
2020-03-30 4:24 ` [PATCH v2 07/22] intel_iommu: add set/unset_iommu_context callback Liu Yi L
2020-03-30 20:23 ` Auger Eric
2020-03-31 12:25 ` Liu, Yi L
2020-03-31 12:57 ` Auger Eric
2020-03-30 4:24 ` [PATCH v2 08/22] vfio/common: provide PASID alloc/free hooks Liu Yi L
2020-03-31 10:47 ` Auger Eric
2020-03-31 10:59 ` Liu, Yi L
2020-03-31 11:15 ` Auger Eric
2020-03-31 12:54 ` Liu, Yi L
2020-03-30 4:24 ` [PATCH v2 09/22] vfio/common: init HostIOMMUContext per-container Liu Yi L
2020-04-01 7:50 ` Auger Eric
2020-04-06 7:12 ` Liu, Yi L
2020-04-06 10:20 ` Auger Eric
2020-04-07 11:59 ` Liu, Yi L
2020-03-30 4:24 ` [PATCH v2 10/22] vfio/pci: set host iommu context to vIOMMU Liu Yi L
2020-03-31 14:30 ` Auger Eric
2020-04-01 3:20 ` Liu, Yi L
2020-03-30 4:24 ` [PATCH v2 11/22] intel_iommu: add virtual command capability support Liu Yi L
2020-03-30 4:24 ` [PATCH v2 12/22] intel_iommu: process PASID cache invalidation Liu Yi L
2020-03-30 4:24 ` [PATCH v2 13/22] intel_iommu: add PASID cache management infrastructure Liu Yi L
2020-04-02 0:02 ` Peter Xu
2020-04-02 6:46 ` Liu, Yi L
2020-04-02 13:44 ` Peter Xu
2020-04-03 15:05 ` Liu, Yi L
2020-04-03 16:19 ` Peter Xu
2020-04-04 11:39 ` Liu, Yi L
2020-03-30 4:24 ` [PATCH v2 14/22] vfio: add bind stage-1 page table support Liu Yi L
2020-03-30 4:24 ` [PATCH v2 15/22] intel_iommu: bind/unbind guest page table to host Liu Yi L
2020-04-02 18:09 ` Peter Xu
2020-04-03 14:29 ` Liu, Yi L
2020-03-30 4:24 ` [PATCH v2 16/22] intel_iommu: replay pasid binds after context cache invalidation Liu Yi L
2020-04-03 14:45 ` Peter Xu
2020-04-03 15:21 ` Liu, Yi L
2020-04-03 16:11 ` Peter Xu
2020-04-04 12:00 ` Liu, Yi L
2020-04-06 19:48 ` Peter Xu
2020-03-30 4:24 ` [PATCH v2 17/22] intel_iommu: do not pass down pasid bind for PASID #0 Liu Yi L
2020-03-30 4:24 ` [PATCH v2 18/22] vfio: add support for flush iommu stage-1 cache Liu Yi L
2020-03-30 4:24 ` [PATCH v2 19/22] intel_iommu: process PASID-based iotlb invalidation Liu Yi L
2020-04-03 14:47 ` Peter Xu
2020-04-03 15:21 ` Liu, Yi L
2020-03-30 4:24 ` [PATCH v2 20/22] intel_iommu: propagate PASID-based iotlb invalidation to host Liu Yi L
2020-03-30 4:25 ` [PATCH v2 21/22] intel_iommu: process PASID-based Device-TLB invalidation Liu Yi L
2020-03-30 4:25 ` Liu Yi L [this message]
2020-04-03 14:49 ` [PATCH v2 22/22] intel_iommu: modify x-scalable-mode to be string option Peter Xu
2020-04-03 15:22 ` Liu, Yi L
2020-03-30 5:40 ` [PATCH v2 00/22] intel_iommu: expose Shared Virtual Addressing to VMs no-reply
2020-03-30 10:36 ` Auger Eric
2020-03-30 14:46 ` Peter Xu
2020-03-31 6:53 ` Liu, Yi L
2020-04-02 8:33 ` Jason Wang
2020-04-02 13:46 ` Peter Xu
2020-04-03 1:38 ` Jason Wang
2020-04-03 14:20 ` Liu, Yi L
2020-04-02 18:12 ` Peter Xu
2020-04-03 14:32 ` Liu, Yi L
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1585542301-84087-23-git-send-email-yi.l.liu@intel.com \
--to=yi.l.liu@intel.com \
--cc=alex.williamson@redhat.com \
--cc=david@gibson.dropbear.id.au \
--cc=ehabkost@redhat.com \
--cc=eric.auger@redhat.com \
--cc=hao.wu@intel.com \
--cc=jacob.jun.pan@linux.intel.com \
--cc=jean-philippe@linaro.org \
--cc=jun.j.tian@intel.com \
--cc=kevin.tian@intel.com \
--cc=kvm@vger.kernel.org \
--cc=mst@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peterx@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=rth@twiddle.net \
--cc=yi.y.sun@intel.com \
--cc=yi.y.sun@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).