* [Qemu devel PATCH v5 0/3] Add SmartFusion2 EMAC block
@ 2020-04-14 15:02 sundeep.lkml
2020-04-14 15:02 ` [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block sundeep.lkml
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: sundeep.lkml @ 2020-04-14 15:02 UTC (permalink / raw)
To: jasowang, peter.maydell, philmd, qemu-devel, qemu-arm; +Cc: Subbaraya Sundeep
From: Subbaraya Sundeep <sundeep.lkml@gmail.com>
This patch set emulates Ethernet MAC block
present in Microsemi SmartFusion2 SoC.
v5:
As per Philippe comments:
Returned size in receive function
Added link property to pass DMA memory
Used FIELD() APIs
Added mac_addr in emac state
Used FIELD_EX32 and FIELD_DP32 APIs
Simplified if else logics in emac_write/read
v4:
Added loop back as per Jason's comment
v3:
Added SmartFusion2 ethernet test to tests/acceptance
v2:
No changes. Fixed Signed-off mail id in patch 2/2
Testing:
1. Download u-boot.bin, uImage and msf2-devkit.dtb from
https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git
2. Copy uImage and msf2-devkit.dtb to suitable Qemu tftp directory
3. Launch Qemu by
./arm-softmmu/qemu-system-arm -M emcraft-sf2 -serial mon:stdio -kernel \
u-boot.bin -display none -nic user,tftp=<qemu tftp directory>
Example:
./arm-softmmu/qemu-system-arm -M emcraft-sf2 -serial mon:stdio -kernel u-boot -display none -nic user,tftp=/home/hyd1358/qemu_tftp
U-Boot 2010.03-00000-ga7695d6 (Apr 04 2020 - 15:07:27)
CPU : SmartFusion2 SoC (Cortex-M3 Hard IP)
Freqs: CORTEX-M3=142MHz,PCLK0=71MHz,PCLK1=71MHz
Board: M2S-FG484-SOM Rev 1A, www.emcraft.com
DRAM: 64 MB
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: M2S_MAC
Hit any key to stop autoboot: 3 0
M2S-FG484-SOM> run netboot
Using M2S_MAC device
TFTP from server 10.0.2.2; our IP address is 10.0.2.15
Filename 'uImage'.
Load address: 0xa0007fc0
Loading: *#################################################################
#################################################################
#################################################################
###############################################################
done
Bytes transferred = 3681568 (382d20 hex)
Using M2S_MAC device
TFTP from server 10.0.2.2; our IP address is 10.0.2.15
Filename 'msf2-devkit.dtb'.
Load address: 0xa0000200
Loading: *#
done
Bytes transferred = 1712 (6b0 hex)
## Booting kernel from Legacy Image at a0007fc0 ...
Image Name:
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 3681504 Bytes = 3.5 MB
Load Address: a0008000
Entry Point: a0008001
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.5.0-gb0e5502-dirty (hyd1358@hyd1358) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-189) ) #85 PREEMPT Sat Apr 4 23:26:40 IST 2020
[ 0.000000] CPU: ARMv7-M [410fc231] revision 1 (ARMv7M), cr=00000000
[ 0.000000] CPU: unknown data cache, unknown instruction cache
[ 0.000000] Machine model: Microsemi SmartFusion 2 development board
[ 0.000000] bootconsole [earlycon0] enabled
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256
[ 0.000000] Kernel command line: console=ttyS0,115200n8 panic=10 mem=64M@0xa0000000 earlyprintk
[ 0.000000] PID hash table entries: 256 (order: -2, 1024 bytes)
[ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Memory: 61212K/65536K available (1612K kernel code, 75K rwdata, 680K rodata, 1224K init, 120K bss, 4324K reserved, 0K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0x00000000 - 0x00001000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0x00000000 - 0xffffffff (4095 MB)
[ 0.000000] lowmem : 0xa0000000 - 0xa4000000 ( 64 MB)
[ 0.000000] modules : 0xa0000000 - 0xa0800000 ( 8 MB)
[ 0.000000] .text : 0xa0008000 - 0xa02453e8 (2293 kB)
[ 0.000000] .init : 0xa0246000 - 0xa0378000 (1224 kB)
[ 0.000000] .data : 0xa0378000 - 0xa038ace0 ( 76 kB)
[ 0.000000] .bss : 0xa038ace0 - 0xa03a8ea0 ( 121 kB)
[ 0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
.
.
.
[ 0.445184] Found M2S MAC at 0x40041000, irq 18
[ 0.448810] libphy: msf2 MII bus: probed
[ 0.527047] ipip: IPv4 over IPv4 tunneling driver
[ 0.532367] NET: Registered protocol family 10
[ 0.542307] sit: IPv6 over IPv4 tunneling driver
[ 0.544655] NET: Registered protocol family 17
[ 0.565395] Freeing unused kernel memory: 1224K (a0246000 - a0378000)
init started: BusyBox v1.31.1 (2020-01-25 20:01:06 IST)
starting pid 26, tty '': '/etc/rc'
starting pid 31, tty '/dev/ttyS0': '/bin/hush -i'
BusyBox v1.31.1 (2020-01-25 20:01:06 IST) hush - the humble shell
Enter 'help' for a list of built-in commands.
/ # ifconfig eth0 10.0.2.15
[ 11.116091] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
/ # [ 11.653634] eth0: link up (100/full)
[ 11.655246] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
/ # ls
dev proc sys etc usr bin tmp sbin mnt init
/ # tftp -gr uImage 10.0.2.2
[ 40.780983] random: nonblocking pool is initialized
/ # ls
dev sys usr tmp mnt uImage
proc etc bin sbin init
/ #
Subbaraya Sundeep (3):
hw/net: Add Smartfusion2 emac block
msf2: Add EMAC block to SmartFusion2 SoC
tests/boot_linux_console: Add ethernet test to SmartFusion2
MAINTAINERS | 2 +
hw/arm/msf2-soc.c | 26 +-
hw/net/Makefile.objs | 1 +
hw/net/msf2-emac.c | 566 +++++++++++++++++++++++++++++++++
include/hw/arm/msf2-soc.h | 2 +
include/hw/net/msf2-emac.h | 53 +++
tests/acceptance/boot_linux_console.py | 15 +-
7 files changed, 658 insertions(+), 7 deletions(-)
create mode 100644 hw/net/msf2-emac.c
create mode 100644 include/hw/net/msf2-emac.h
--
2.7.4
^ permalink raw reply [flat|nested] 6+ messages in thread* [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block 2020-04-14 15:02 [Qemu devel PATCH v5 0/3] Add SmartFusion2 EMAC block sundeep.lkml @ 2020-04-14 15:02 ` sundeep.lkml 2020-04-15 6:13 ` Philippe Mathieu-Daudé 2020-04-14 15:02 ` [Qemu devel PATCH v5 2/3] msf2: Add EMAC block to SmartFusion2 SoC sundeep.lkml 2020-04-14 15:02 ` [Qemu devel PATCH v5 3/3] tests/boot_linux_console: Add ethernet test to SmartFusion2 sundeep.lkml 2 siblings, 1 reply; 6+ messages in thread From: sundeep.lkml @ 2020-04-14 15:02 UTC (permalink / raw) To: jasowang, peter.maydell, philmd, qemu-devel, qemu-arm; +Cc: Subbaraya Sundeep From: Subbaraya Sundeep <sundeep.lkml@gmail.com> Modelled Ethernet MAC of Smartfusion2 SoC. Micrel KSZ8051 PHY is present on Emcraft's SOM kit hence same PHY is emulated. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- MAINTAINERS | 2 + hw/net/Makefile.objs | 1 + hw/net/msf2-emac.c | 566 +++++++++++++++++++++++++++++++++++++++++++++ include/hw/net/msf2-emac.h | 53 +++++ 4 files changed, 622 insertions(+) create mode 100644 hw/net/msf2-emac.c create mode 100644 include/hw/net/msf2-emac.h diff --git a/MAINTAINERS b/MAINTAINERS index 642c8e0..9d0ff20 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -919,6 +919,8 @@ F: include/hw/arm/msf2-soc.h F: include/hw/misc/msf2-sysreg.h F: include/hw/timer/mss-timer.h F: include/hw/ssi/mss-spi.h +F: hw/net/msf2-emac.c +F: include/hw/net/msf2-emac.h Emcraft M2S-FG484 M: Subbaraya Sundeep <sundeep.lkml@gmail.com> diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs index af4d194..f2b7398 100644 --- a/hw/net/Makefile.objs +++ b/hw/net/Makefile.objs @@ -55,3 +55,4 @@ common-obj-$(CONFIG_ROCKER) += rocker/rocker.o rocker/rocker_fp.o \ obj-$(call lnot,$(CONFIG_ROCKER)) += rocker/qmp-norocker.o common-obj-$(CONFIG_CAN_BUS) += can/ +common-obj-$(CONFIG_MSF2) += msf2-emac.o diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c new file mode 100644 index 0000000..cae40fd --- /dev/null +++ b/hw/net/msf2-emac.c @@ -0,0 +1,566 @@ +/* + * QEMU model of the Smartfusion2 Ethernet MAC. + * + * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * Refer to section Ethernet MAC in the document: + * UG0331: SmartFusion2 Microcontroller Subsystem User Guide + * Datasheet URL: + * https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/ + * 56758-soc?lang=en&limit=20&limitstart=220 + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "hw/registerfields.h" +#include "hw/net/msf2-emac.h" +#include "hw/net/mii.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +REG32(CFG1, 0x0) + FIELD(CFG1, RESET, 31, 1) + FIELD(CFG1, RX_EN, 2, 1) + FIELD(CFG1, TX_EN, 0, 1) + FIELD(CFG1, LB_EN, 8, 1) +REG32(CFG2, 0x4) +REG32(IFG, 0x8) +REG32(HALF_DUPLEX, 0xc) +REG32(MAX_FRAME_LENGTH, 0x10) +REG32(MII_CMD, 0x24) + FIELD(MII_CMD, READ, 0, 1) +REG32(MII_ADDR, 0x28) + FIELD(MII_ADDR, REGADDR, 0, 5) + FIELD(MII_ADDR, PHYADDR, 8, 5) +REG32(MII_CTL, 0x2c) +REG32(MII_STS, 0x30) +REG32(STA1, 0x40) +REG32(STA2, 0x44) +REG32(FIFO_CFG0, 0x48) +REG32(DMA_TX_CTL, 0x180) + FIELD(DMA_TX_CTL, EN, 0, 1) +REG32(DMA_TX_DESC, 0x184) +REG32(DMA_TX_STATUS, 0x188) + FIELD(DMA_TX_STATUS, PKTCNT, 16, 8) + FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1) + FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1) +REG32(DMA_RX_CTL, 0x18c) + FIELD(DMA_RX_CTL, EN, 0, 1) +REG32(DMA_RX_DESC, 0x190) +REG32(DMA_RX_STATUS, 0x194) + FIELD(DMA_RX_STATUS, PKTCNT, 16, 8) + FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1) + FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1) +REG32(DMA_IRQ_MASK, 0x198) +REG32(DMA_IRQ, 0x19c) + +#define EMPTY_MASK (1 << 31) +#define PKT_SIZE 0x7FF +#define PHYADDR 0x1 +#define MAX_PKT_SIZE 2048 + +typedef struct { + uint32_t pktaddr; + uint32_t pktsize; + uint32_t next; +} EmacDesc; + +static uint32_t emac_get_isr(MSF2EmacState *s) +{ + uint32_t ier = s->regs[R_DMA_IRQ_MASK]; + uint32_t tx = s->regs[R_DMA_TX_STATUS] & 0xF; + uint32_t rx = s->regs[R_DMA_RX_STATUS] & 0xF; + uint32_t isr = (rx << 4) | tx; + + s->regs[R_DMA_IRQ] = ier & isr; + return s->regs[R_DMA_IRQ]; +} + +static void emac_update_irq(MSF2EmacState *s) +{ + bool intr = emac_get_isr(s); + + qemu_set_irq(s->irq, intr); +} + +static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) +{ + address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); + /* Convert from LE into host endianness. */ + d->pktaddr = le32_to_cpu(d->pktaddr); + d->pktsize = le32_to_cpu(d->pktsize); + d->next = le32_to_cpu(d->next); +} + +static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) +{ + /* Convert from host endianness into LE. */ + d->pktaddr = cpu_to_le32(d->pktaddr); + d->pktsize = cpu_to_le32(d->pktsize); + d->next = cpu_to_le32(d->next); + + address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); +} + +static void msf2_dma_tx(MSF2EmacState *s) +{ + NetClientState *nc = qemu_get_queue(s->nic); + hwaddr desc = s->regs[R_DMA_TX_DESC]; + uint8_t buf[MAX_PKT_SIZE]; + EmacDesc d; + int size; + uint8_t pktcnt; + uint32_t status; + + if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) { + return; + } + + while (1) { + emac_load_desc(s, &d, desc); + if (d.pktsize & EMPTY_MASK) { + break; + } + size = d.pktsize & PKT_SIZE; + address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, + buf, size); + /* + * This is very basic way to send packets. Ideally there should be + * a FIFO and packets should be sent out from FIFO only when + * R_CFG1 bit 0 is set. + */ + if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) { + nc->info->receive(nc, buf, size); + } else { + qemu_send_packet(nc, buf, size); + } + d.pktsize |= EMPTY_MASK; + emac_store_desc(s, &d, desc); + /* update sent packets count */ + status = s->regs[R_DMA_TX_STATUS]; + pktcnt = FIELD_EX32(status, DMA_TX_STATUS, PKTCNT); + pktcnt++; + s->regs[R_DMA_TX_STATUS] = FIELD_DP32(status, DMA_TX_STATUS, + PKTCNT, pktcnt); + s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_PKT_SENT_MASK; + desc = d.next; + } + s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_UNDERRUN_MASK; + s->regs[R_DMA_TX_CTL] &= ~R_DMA_TX_CTL_EN_MASK; +} + +static void msf2_phy_update_link(MSF2EmacState *s) +{ + /* Autonegotiation status mirrors link status. */ + if (qemu_get_queue(s->nic)->link_down) { + s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP | + MII_BMSR_LINK_ST); + } else { + s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP | + MII_BMSR_LINK_ST); + } +} + +static void msf2_phy_reset(MSF2EmacState *s) +{ + memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); + s->phy_regs[MII_BMCR] = 0x1140; + s->phy_regs[MII_BMSR] = 0x7968; + s->phy_regs[MII_PHYID1] = 0x0022; + s->phy_regs[MII_PHYID2] = 0x1550; + s->phy_regs[MII_ANAR] = 0x01E1; + s->phy_regs[MII_ANLPAR] = 0xCDE1; + + msf2_phy_update_link(s); +} + +static void write_to_phy(MSF2EmacState *s) +{ + uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; + uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & + R_MII_ADDR_REGADDR_MASK; + uint16_t data = s->regs[R_MII_CTL] & 0xFFFF; + + if (phy_addr != PHYADDR) { + return; + } + + switch (reg_addr) { + case MII_BMCR: + if (data & MII_BMCR_RESET) { + /* Phy reset */ + msf2_phy_reset(s); + data &= ~MII_BMCR_RESET; + } + if (data & MII_BMCR_AUTOEN) { + /* Complete autonegotiation immediately */ + data &= ~MII_BMCR_AUTOEN; + s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP; + } + break; + } + + s->phy_regs[reg_addr] = data; +} + +static uint16_t read_from_phy(MSF2EmacState *s) +{ + uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; + uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & + R_MII_ADDR_REGADDR_MASK; + + if (phy_addr == PHYADDR) { + return s->phy_regs[reg_addr]; + } else { + return 0xFFFF; + } +} + +static void msf2_emac_do_reset(MSF2EmacState *s) +{ + memset(&s->regs[0], 0, sizeof(s->regs)); + s->regs[R_CFG1] = 0x80000000; + s->regs[R_CFG2] = 0x00007000; + s->regs[R_IFG] = 0x40605060; + s->regs[R_HALF_DUPLEX] = 0x00A1F037; + s->regs[R_MAX_FRAME_LENGTH] = 0x00000600; + + msf2_phy_reset(s); +} + +static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size) +{ + MSF2EmacState *s = opaque; + uint32_t r = 0; + + addr >>= 2; + + switch (addr) { + case R_DMA_IRQ: + r = emac_get_isr(s); + break; + default: + if (addr >= ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + return r; + } + r = s->regs[addr]; + break; + } + return r; +} + +static void emac_write(void *opaque, hwaddr addr, uint64_t val64, + unsigned int size) +{ + MSF2EmacState *s = opaque; + uint32_t value = val64; + uint32_t enreqbits; + uint8_t pktcnt; + + addr >>= 2; + switch (addr) { + case R_DMA_TX_CTL: + s->regs[addr] = value; + if (value & R_DMA_TX_CTL_EN_MASK) { + msf2_dma_tx(s); + } + break; + case R_DMA_RX_CTL: + s->regs[addr] = value; + if (value & R_DMA_RX_CTL_EN_MASK) { + s->rx_desc = s->regs[R_DMA_RX_DESC]; + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } + break; + case R_CFG1: + if (value & R_CFG1_RESET_MASK) { + msf2_emac_do_reset(s); + } + case R_FIFO_CFG0: + /* + * For our implementation, turning on modules is instantaneous, + * so the states requested via the *ENREQ bits appear in the + * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC + * module are not emulated here since it deals with start of frames, + * inter-packet gap and control frames. + */ + enreqbits = extract32(value, 8, 5); + s->regs[addr] = deposit32(value, 16, 5, enreqbits); + break; + case R_DMA_TX_DESC: + if (value & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should be" + " 32 bit aligned\n"); + } + /* Ignore [1:0] bits */ + s->regs[addr] = value & ~3; + break; + case R_DMA_RX_DESC: + if (value & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should be" + " 32 bit aligned\n"); + } + /* Ignore [1:0] bits */ + s->regs[addr] = value & ~3; + break; + case R_DMA_TX_STATUS: + if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) { + s->regs[addr] &= ~R_DMA_TX_STATUS_UNDERRUN_MASK; + } + if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) { + pktcnt = FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT); + pktcnt--; + s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_TX_STATUS, + PKTCNT, pktcnt); + if (pktcnt == 0) { + s->regs[addr] &= ~R_DMA_TX_STATUS_PKT_SENT_MASK; + } + } + break; + case R_DMA_RX_STATUS: + if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) { + s->regs[addr] &= ~R_DMA_RX_STATUS_OVERFLOW_MASK; + } + if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) { + pktcnt = FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT); + pktcnt--; + s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_RX_STATUS, + PKTCNT, pktcnt); + if (pktcnt == 0) { + s->regs[addr] &= ~R_DMA_RX_STATUS_PKT_RCVD_MASK; + } + } + break; + case R_DMA_IRQ: + break; + case R_MII_CMD: + if (value & R_MII_CMD_READ_MASK) { + s->regs[R_MII_STS] = read_from_phy(s); + } + break; + case R_MII_CTL: + s->regs[addr] = value; + write_to_phy(s); + break; + case R_STA1: + s->regs[addr] = value; + /* + * R_STA1 [31:24] : octet 1 of mac address + * R_STA1 [23:16] : octet 2 of mac address + * R_STA1 [15:8] : octet 3 of mac address + * R_STA1 [7:0] : octet 4 of mac address + */ + stl_le_p(s->mac_addr, value); + break; + case R_STA2: + s->regs[addr] = value; + /* + * R_STA2 [31:24] : octet 5 of mac address + * R_STA2 [23:16] : octet 6 of mac address + */ + stw_le_p(s->mac_addr + 4, value >> 16); + break; + default: + if (addr >= ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + return; + } + s->regs[addr] = value; + break; + } + emac_update_irq(s); +} + +static const MemoryRegionOps emac_ops = { + .read = emac_read, + .write = emac_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static bool emac_can_rx(NetClientState *nc) +{ + MSF2EmacState *s = qemu_get_nic_opaque(nc); + + return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) && + (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK); +} + +static bool match_addr(MSF2EmacState *s, const uint8_t *buf) +{ + /* The broadcast MAC address: FF:FF:FF:FF:FF:FF */ + static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF }; + + if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) { + return true; + } + + if (!memcmp(buf, s->mac_addr, sizeof(s->mac_addr))) { + return false; + } + + return true; +} + +static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size) +{ + MSF2EmacState *s = qemu_get_nic_opaque(nc); + EmacDesc d; + uint8_t pktcnt; + uint32_t status; + + if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) { + return size; + } + if (!match_addr(s, buf)) { + return size; + } + + emac_load_desc(s, &d, s->rx_desc); + + if (d.pktsize & EMPTY_MASK) { + address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, + buf, size & PKT_SIZE); + d.pktsize = size & PKT_SIZE; + emac_store_desc(s, &d, s->rx_desc); + /* update received packets count */ + status = s->regs[R_DMA_RX_STATUS]; + pktcnt = FIELD_EX32(status, DMA_RX_STATUS, PKTCNT); + pktcnt++; + s->regs[R_DMA_RX_STATUS] = FIELD_DP32(status, DMA_RX_STATUS, + PKTCNT, pktcnt); + s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_PKT_RCVD_MASK; + s->rx_desc = d.next; + } else { + s->regs[R_DMA_RX_CTL] &= ~R_DMA_RX_CTL_EN_MASK; + s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_OVERFLOW_MASK; + } + emac_update_irq(s); + return size; +} + +static void msf2_emac_reset(DeviceState *dev) +{ + MSF2EmacState *s = MSS_EMAC(dev); + + msf2_emac_do_reset(s); +} + +static void emac_set_link(NetClientState *nc) +{ + MSF2EmacState *s = qemu_get_nic_opaque(nc); + + msf2_phy_update_link(s); +} + +static NetClientInfo net_msf2_emac_info = { + .type = NET_CLIENT_DRIVER_NIC, + .size = sizeof(NICState), + .can_receive = emac_can_rx, + .receive = emac_rx, + .link_status_changed = emac_set_link, +}; + +static void msf2_emac_realize(DeviceState *dev, Error **errp) +{ + MSF2EmacState *s = MSS_EMAC(dev); + + if (!s->dma_mr) { + error_setg(errp, "MSS_EMAC 'ahb-bus' link not set"); + return; + } + + address_space_init(&s->dma_as, s->dma_mr, "emac-ahb"); + + qemu_macaddr_default_if_unset(&s->conf.macaddr); + s->nic = qemu_new_nic(&net_msf2_emac_info, &s->conf, + object_get_typename(OBJECT(dev)), dev->id, s); + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); +} + +static void msf2_emac_init(Object *obj) +{ + MSF2EmacState *s = MSS_EMAC(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &emac_ops, s, + "msf2-emac", R_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static Property msf2_emac_properties[] = { + DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_NIC_PROPERTIES(MSF2EmacState, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_msf2_emac = { + .name = TYPE_MSS_EMAC, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN), + VMSTATE_UINT32(rx_desc, MSF2EmacState), + VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS), + VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static void msf2_emac_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = msf2_emac_realize; + dc->reset = msf2_emac_reset; + dc->vmsd = &vmstate_msf2_emac; + device_class_set_props(dc, msf2_emac_properties); +} + +static const TypeInfo msf2_emac_info = { + .name = TYPE_MSS_EMAC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(MSF2EmacState), + .instance_init = msf2_emac_init, + .class_init = msf2_emac_class_init, +}; + +static void msf2_emac_register_types(void) +{ + type_register_static(&msf2_emac_info); +} + +type_init(msf2_emac_register_types) diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h new file mode 100644 index 0000000..37966d3 --- /dev/null +++ b/include/hw/net/msf2-emac.h @@ -0,0 +1,53 @@ +/* + * QEMU model of the Smartfusion2 Ethernet MAC. + * + * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hw/sysbus.h" +#include "exec/memory.h" +#include "net/net.h" +#include "net/eth.h" + +#define TYPE_MSS_EMAC "msf2-emac" +#define MSS_EMAC(obj) \ + OBJECT_CHECK(MSF2EmacState, (obj), TYPE_MSS_EMAC) + +#define R_MAX (0x1a0 / 4) +#define PHY_MAX_REGS 32 + +typedef struct MSF2EmacState { + SysBusDevice parent; + + MemoryRegion mmio; + MemoryRegion *dma_mr; + AddressSpace dma_as; + + qemu_irq irq; + NICState *nic; + NICConf conf; + + uint8_t mac_addr[ETH_ALEN]; + uint32_t rx_desc; + uint16_t phy_regs[PHY_MAX_REGS]; + + uint32_t regs[R_MAX]; +} MSF2EmacState; -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block 2020-04-14 15:02 ` [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block sundeep.lkml @ 2020-04-15 6:13 ` Philippe Mathieu-Daudé 2020-04-15 10:59 ` sundeep subbaraya 0 siblings, 1 reply; 6+ messages in thread From: Philippe Mathieu-Daudé @ 2020-04-15 6:13 UTC (permalink / raw) To: sundeep.lkml, jasowang, peter.maydell, philmd, qemu-devel, qemu-arm On 4/14/20 5:02 PM, sundeep.lkml@gmail.com wrote: > From: Subbaraya Sundeep <sundeep.lkml@gmail.com> > > Modelled Ethernet MAC of Smartfusion2 SoC. > Micrel KSZ8051 PHY is present on Emcraft's > SOM kit hence same PHY is emulated. > > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > MAINTAINERS | 2 + > hw/net/Makefile.objs | 1 + > hw/net/msf2-emac.c | 566 +++++++++++++++++++++++++++++++++++++++++++++ > include/hw/net/msf2-emac.h | 53 +++++ > 4 files changed, 622 insertions(+) > create mode 100644 hw/net/msf2-emac.c > create mode 100644 include/hw/net/msf2-emac.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 642c8e0..9d0ff20 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -919,6 +919,8 @@ F: include/hw/arm/msf2-soc.h > F: include/hw/misc/msf2-sysreg.h > F: include/hw/timer/mss-timer.h > F: include/hw/ssi/mss-spi.h > +F: hw/net/msf2-emac.c > +F: include/hw/net/msf2-emac.h > > Emcraft M2S-FG484 > M: Subbaraya Sundeep <sundeep.lkml@gmail.com> > diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs > index af4d194..f2b7398 100644 > --- a/hw/net/Makefile.objs > +++ b/hw/net/Makefile.objs > @@ -55,3 +55,4 @@ common-obj-$(CONFIG_ROCKER) += rocker/rocker.o rocker/rocker_fp.o \ > obj-$(call lnot,$(CONFIG_ROCKER)) += rocker/qmp-norocker.o > > common-obj-$(CONFIG_CAN_BUS) += can/ > +common-obj-$(CONFIG_MSF2) += msf2-emac.o > diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c > new file mode 100644 > index 0000000..cae40fd > --- /dev/null > +++ b/hw/net/msf2-emac.c > @@ -0,0 +1,566 @@ > +/* > + * QEMU model of the Smartfusion2 Ethernet MAC. > + * > + * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + * > + * Refer to section Ethernet MAC in the document: > + * UG0331: SmartFusion2 Microcontroller Subsystem User Guide > + * Datasheet URL: > + * https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/ > + * 56758-soc?lang=en&limit=20&limitstart=220 > + */ > + > +#include "qemu/osdep.h" > +#include "qemu-common.h" > +#include "qemu/log.h" > +#include "qapi/error.h" > +#include "exec/address-spaces.h" > +#include "hw/registerfields.h" > +#include "hw/net/msf2-emac.h" > +#include "hw/net/mii.h" > +#include "hw/irq.h" > +#include "hw/qdev-properties.h" > +#include "migration/vmstate.h" > + > +REG32(CFG1, 0x0) > + FIELD(CFG1, RESET, 31, 1) > + FIELD(CFG1, RX_EN, 2, 1) > + FIELD(CFG1, TX_EN, 0, 1) > + FIELD(CFG1, LB_EN, 8, 1) > +REG32(CFG2, 0x4) > +REG32(IFG, 0x8) > +REG32(HALF_DUPLEX, 0xc) > +REG32(MAX_FRAME_LENGTH, 0x10) > +REG32(MII_CMD, 0x24) > + FIELD(MII_CMD, READ, 0, 1) > +REG32(MII_ADDR, 0x28) > + FIELD(MII_ADDR, REGADDR, 0, 5) > + FIELD(MII_ADDR, PHYADDR, 8, 5) > +REG32(MII_CTL, 0x2c) > +REG32(MII_STS, 0x30) > +REG32(STA1, 0x40) > +REG32(STA2, 0x44) > +REG32(FIFO_CFG0, 0x48) > +REG32(DMA_TX_CTL, 0x180) > + FIELD(DMA_TX_CTL, EN, 0, 1) > +REG32(DMA_TX_DESC, 0x184) > +REG32(DMA_TX_STATUS, 0x188) > + FIELD(DMA_TX_STATUS, PKTCNT, 16, 8) > + FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1) > + FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1) > +REG32(DMA_RX_CTL, 0x18c) > + FIELD(DMA_RX_CTL, EN, 0, 1) > +REG32(DMA_RX_DESC, 0x190) > +REG32(DMA_RX_STATUS, 0x194) > + FIELD(DMA_RX_STATUS, PKTCNT, 16, 8) > + FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1) > + FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1) > +REG32(DMA_IRQ_MASK, 0x198) > +REG32(DMA_IRQ, 0x19c) > + > +#define EMPTY_MASK (1 << 31) > +#define PKT_SIZE 0x7FF > +#define PHYADDR 0x1 > +#define MAX_PKT_SIZE 2048 > + > +typedef struct { > + uint32_t pktaddr; > + uint32_t pktsize; > + uint32_t next; > +} EmacDesc; > + > +static uint32_t emac_get_isr(MSF2EmacState *s) > +{ > + uint32_t ier = s->regs[R_DMA_IRQ_MASK]; > + uint32_t tx = s->regs[R_DMA_TX_STATUS] & 0xF; > + uint32_t rx = s->regs[R_DMA_RX_STATUS] & 0xF; > + uint32_t isr = (rx << 4) | tx; > + > + s->regs[R_DMA_IRQ] = ier & isr; > + return s->regs[R_DMA_IRQ]; > +} > + > +static void emac_update_irq(MSF2EmacState *s) > +{ > + bool intr = emac_get_isr(s); > + > + qemu_set_irq(s->irq, intr); > +} > + > +static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) > +{ > + address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); > + /* Convert from LE into host endianness. */ > + d->pktaddr = le32_to_cpu(d->pktaddr); > + d->pktsize = le32_to_cpu(d->pktsize); > + d->next = le32_to_cpu(d->next); > +} > + > +static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) > +{ > + /* Convert from host endianness into LE. */ > + d->pktaddr = cpu_to_le32(d->pktaddr); > + d->pktsize = cpu_to_le32(d->pktsize); > + d->next = cpu_to_le32(d->next); > + > + address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); > +} > + > +static void msf2_dma_tx(MSF2EmacState *s) > +{ > + NetClientState *nc = qemu_get_queue(s->nic); > + hwaddr desc = s->regs[R_DMA_TX_DESC]; > + uint8_t buf[MAX_PKT_SIZE]; > + EmacDesc d; > + int size; > + uint8_t pktcnt; > + uint32_t status; > + > + if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) { > + return; > + } > + > + while (1) { > + emac_load_desc(s, &d, desc); > + if (d.pktsize & EMPTY_MASK) { > + break; > + } > + size = d.pktsize & PKT_SIZE; > + address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, > + buf, size); > + /* > + * This is very basic way to send packets. Ideally there should be > + * a FIFO and packets should be sent out from FIFO only when > + * R_CFG1 bit 0 is set. > + */ > + if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) { > + nc->info->receive(nc, buf, size); > + } else { > + qemu_send_packet(nc, buf, size); > + } > + d.pktsize |= EMPTY_MASK; > + emac_store_desc(s, &d, desc); > + /* update sent packets count */ > + status = s->regs[R_DMA_TX_STATUS]; > + pktcnt = FIELD_EX32(status, DMA_TX_STATUS, PKTCNT); > + pktcnt++; > + s->regs[R_DMA_TX_STATUS] = FIELD_DP32(status, DMA_TX_STATUS, > + PKTCNT, pktcnt); > + s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_PKT_SENT_MASK; > + desc = d.next; > + } > + s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_UNDERRUN_MASK; > + s->regs[R_DMA_TX_CTL] &= ~R_DMA_TX_CTL_EN_MASK; > +} > + > +static void msf2_phy_update_link(MSF2EmacState *s) > +{ > + /* Autonegotiation status mirrors link status. */ > + if (qemu_get_queue(s->nic)->link_down) { > + s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP | > + MII_BMSR_LINK_ST); > + } else { > + s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP | > + MII_BMSR_LINK_ST); > + } > +} > + > +static void msf2_phy_reset(MSF2EmacState *s) > +{ > + memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); > + s->phy_regs[MII_BMCR] = 0x1140; > + s->phy_regs[MII_BMSR] = 0x7968; > + s->phy_regs[MII_PHYID1] = 0x0022; > + s->phy_regs[MII_PHYID2] = 0x1550; > + s->phy_regs[MII_ANAR] = 0x01E1; > + s->phy_regs[MII_ANLPAR] = 0xCDE1; > + > + msf2_phy_update_link(s); > +} > + > +static void write_to_phy(MSF2EmacState *s) > +{ > + uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; > + uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & > + R_MII_ADDR_REGADDR_MASK; > + uint16_t data = s->regs[R_MII_CTL] & 0xFFFF; > + > + if (phy_addr != PHYADDR) { > + return; > + } > + > + switch (reg_addr) { > + case MII_BMCR: > + if (data & MII_BMCR_RESET) { > + /* Phy reset */ > + msf2_phy_reset(s); > + data &= ~MII_BMCR_RESET; > + } > + if (data & MII_BMCR_AUTOEN) { > + /* Complete autonegotiation immediately */ > + data &= ~MII_BMCR_AUTOEN; > + s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP; > + } > + break; > + } > + > + s->phy_regs[reg_addr] = data; > +} > + > +static uint16_t read_from_phy(MSF2EmacState *s) > +{ > + uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; > + uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & > + R_MII_ADDR_REGADDR_MASK; > + > + if (phy_addr == PHYADDR) { > + return s->phy_regs[reg_addr]; > + } else { > + return 0xFFFF; > + } > +} > + > +static void msf2_emac_do_reset(MSF2EmacState *s) > +{ > + memset(&s->regs[0], 0, sizeof(s->regs)); > + s->regs[R_CFG1] = 0x80000000; > + s->regs[R_CFG2] = 0x00007000; > + s->regs[R_IFG] = 0x40605060; > + s->regs[R_HALF_DUPLEX] = 0x00A1F037; > + s->regs[R_MAX_FRAME_LENGTH] = 0x00000600; > + > + msf2_phy_reset(s); > +} > + > +static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size) > +{ > + MSF2EmacState *s = opaque; > + uint32_t r = 0; > + > + addr >>= 2; > + > + switch (addr) { > + case R_DMA_IRQ: > + r = emac_get_isr(s); > + break; > + default: > + if (addr >= ARRAY_SIZE(s->regs)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, > + addr * 4); > + return r; > + } > + r = s->regs[addr]; > + break; > + } > + return r; > +} > + > +static void emac_write(void *opaque, hwaddr addr, uint64_t val64, > + unsigned int size) > +{ > + MSF2EmacState *s = opaque; > + uint32_t value = val64; > + uint32_t enreqbits; > + uint8_t pktcnt; > + > + addr >>= 2; > + switch (addr) { > + case R_DMA_TX_CTL: > + s->regs[addr] = value; > + if (value & R_DMA_TX_CTL_EN_MASK) { > + msf2_dma_tx(s); > + } > + break; > + case R_DMA_RX_CTL: > + s->regs[addr] = value; > + if (value & R_DMA_RX_CTL_EN_MASK) { > + s->rx_desc = s->regs[R_DMA_RX_DESC]; > + qemu_flush_queued_packets(qemu_get_queue(s->nic)); > + } > + break; > + case R_CFG1: > + if (value & R_CFG1_RESET_MASK) { > + msf2_emac_do_reset(s); > + } Missing break? > + case R_FIFO_CFG0: > + /* > + * For our implementation, turning on modules is instantaneous, > + * so the states requested via the *ENREQ bits appear in the > + * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC > + * module are not emulated here since it deals with start of frames, > + * inter-packet gap and control frames. > + */ > + enreqbits = extract32(value, 8, 5); > + s->regs[addr] = deposit32(value, 16, 5, enreqbits); > + break; > + case R_DMA_TX_DESC: > + if (value & 0x3) { > + qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should be" > + " 32 bit aligned\n"); > + } > + /* Ignore [1:0] bits */ > + s->regs[addr] = value & ~3; > + break; > + case R_DMA_RX_DESC: > + if (value & 0x3) { > + qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should be" > + " 32 bit aligned\n"); > + } > + /* Ignore [1:0] bits */ > + s->regs[addr] = value & ~3; > + break; > + case R_DMA_TX_STATUS: > + if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) { > + s->regs[addr] &= ~R_DMA_TX_STATUS_UNDERRUN_MASK; > + } > + if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) { > + pktcnt = FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT); > + pktcnt--; > + s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_TX_STATUS, > + PKTCNT, pktcnt); > + if (pktcnt == 0) { > + s->regs[addr] &= ~R_DMA_TX_STATUS_PKT_SENT_MASK; > + } > + } > + break; > + case R_DMA_RX_STATUS: > + if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) { > + s->regs[addr] &= ~R_DMA_RX_STATUS_OVERFLOW_MASK; > + } > + if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) { > + pktcnt = FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT); > + pktcnt--; > + s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_RX_STATUS, > + PKTCNT, pktcnt); > + if (pktcnt == 0) { > + s->regs[addr] &= ~R_DMA_RX_STATUS_PKT_RCVD_MASK; > + } > + } > + break; > + case R_DMA_IRQ: > + break; > + case R_MII_CMD: > + if (value & R_MII_CMD_READ_MASK) { > + s->regs[R_MII_STS] = read_from_phy(s); > + } > + break; > + case R_MII_CTL: > + s->regs[addr] = value; > + write_to_phy(s); > + break; > + case R_STA1: > + s->regs[addr] = value; > + /* > + * R_STA1 [31:24] : octet 1 of mac address > + * R_STA1 [23:16] : octet 2 of mac address > + * R_STA1 [15:8] : octet 3 of mac address > + * R_STA1 [7:0] : octet 4 of mac address > + */ > + stl_le_p(s->mac_addr, value); > + break; > + case R_STA2: > + s->regs[addr] = value; > + /* > + * R_STA2 [31:24] : octet 5 of mac address > + * R_STA2 [23:16] : octet 6 of mac address > + */ > + stw_le_p(s->mac_addr + 4, value >> 16); > + break; > + default: > + if (addr >= ARRAY_SIZE(s->regs)) { > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, > + addr * 4); > + return; > + } > + s->regs[addr] = value; > + break; > + } > + emac_update_irq(s); > +} > + > +static const MemoryRegionOps emac_ops = { > + .read = emac_read, > + .write = emac_write, > + .endianness = DEVICE_NATIVE_ENDIAN, > + .impl = { > + .min_access_size = 4, > + .max_access_size = 4 > + } > +}; > + > +static bool emac_can_rx(NetClientState *nc) > +{ > + MSF2EmacState *s = qemu_get_nic_opaque(nc); > + > + return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) && > + (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK); > +} > + > +static bool match_addr(MSF2EmacState *s, const uint8_t *buf) > +{ > + /* The broadcast MAC address: FF:FF:FF:FF:FF:FF */ > + static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, > + 0xFF, 0xFF }; > + > + if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) { > + return true; > + } > + > + if (!memcmp(buf, s->mac_addr, sizeof(s->mac_addr))) { > + return false; > + } > + > + return true; Yes, or: return !!memcmp(buf, s->mac_addr, sizeof(s->mac_addr)); > +} > + > +static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size) > +{ > + MSF2EmacState *s = qemu_get_nic_opaque(nc); > + EmacDesc d; > + uint8_t pktcnt; > + uint32_t status; > + > + if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) { > + return size; > + } > + if (!match_addr(s, buf)) { > + return size; > + } > + > + emac_load_desc(s, &d, s->rx_desc); > + > + if (d.pktsize & EMPTY_MASK) { > + address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, > + buf, size & PKT_SIZE); > + d.pktsize = size & PKT_SIZE; > + emac_store_desc(s, &d, s->rx_desc); > + /* update received packets count */ > + status = s->regs[R_DMA_RX_STATUS]; > + pktcnt = FIELD_EX32(status, DMA_RX_STATUS, PKTCNT); > + pktcnt++; > + s->regs[R_DMA_RX_STATUS] = FIELD_DP32(status, DMA_RX_STATUS, > + PKTCNT, pktcnt); > + s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_PKT_RCVD_MASK; > + s->rx_desc = d.next; > + } else { > + s->regs[R_DMA_RX_CTL] &= ~R_DMA_RX_CTL_EN_MASK; > + s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_OVERFLOW_MASK; > + } > + emac_update_irq(s); > + return size; > +} > + > +static void msf2_emac_reset(DeviceState *dev) > +{ > + MSF2EmacState *s = MSS_EMAC(dev); > + > + msf2_emac_do_reset(s); > +} > + > +static void emac_set_link(NetClientState *nc) > +{ > + MSF2EmacState *s = qemu_get_nic_opaque(nc); > + > + msf2_phy_update_link(s); > +} > + > +static NetClientInfo net_msf2_emac_info = { > + .type = NET_CLIENT_DRIVER_NIC, > + .size = sizeof(NICState), > + .can_receive = emac_can_rx, > + .receive = emac_rx, > + .link_status_changed = emac_set_link, > +}; > + > +static void msf2_emac_realize(DeviceState *dev, Error **errp) > +{ > + MSF2EmacState *s = MSS_EMAC(dev); > + > + if (!s->dma_mr) { > + error_setg(errp, "MSS_EMAC 'ahb-bus' link not set"); > + return; > + } > + > + address_space_init(&s->dma_as, s->dma_mr, "emac-ahb"); > + > + qemu_macaddr_default_if_unset(&s->conf.macaddr); > + s->nic = qemu_new_nic(&net_msf2_emac_info, &s->conf, > + object_get_typename(OBJECT(dev)), dev->id, s); > + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); > +} > + > +static void msf2_emac_init(Object *obj) > +{ > + MSF2EmacState *s = MSS_EMAC(obj); > + > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); > + > + memory_region_init_io(&s->mmio, obj, &emac_ops, s, > + "msf2-emac", R_MAX * 4); > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > +} > + > +static Property msf2_emac_properties[] = { > + DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr, > + TYPE_MEMORY_REGION, MemoryRegion *), > + DEFINE_NIC_PROPERTIES(MSF2EmacState, conf), > + DEFINE_PROP_END_OF_LIST(), > +}; > + > +static const VMStateDescription vmstate_msf2_emac = { > + .name = TYPE_MSS_EMAC, > + .version_id = 1, > + .minimum_version_id = 1, > + .fields = (VMStateField[]) { > + VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN), > + VMSTATE_UINT32(rx_desc, MSF2EmacState), > + VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS), > + VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX), > + VMSTATE_END_OF_LIST() > + } > +}; > + > +static void msf2_emac_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc = DEVICE_CLASS(klass); > + > + dc->realize = msf2_emac_realize; > + dc->reset = msf2_emac_reset; > + dc->vmsd = &vmstate_msf2_emac; > + device_class_set_props(dc, msf2_emac_properties); > +} > + > +static const TypeInfo msf2_emac_info = { > + .name = TYPE_MSS_EMAC, > + .parent = TYPE_SYS_BUS_DEVICE, > + .instance_size = sizeof(MSF2EmacState), > + .instance_init = msf2_emac_init, > + .class_init = msf2_emac_class_init, > +}; > + > +static void msf2_emac_register_types(void) > +{ > + type_register_static(&msf2_emac_info); > +} > + > +type_init(msf2_emac_register_types) > diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h > new file mode 100644 > index 0000000..37966d3 > --- /dev/null > +++ b/include/hw/net/msf2-emac.h > @@ -0,0 +1,53 @@ > +/* > + * QEMU model of the Smartfusion2 Ethernet MAC. > + * > + * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "hw/sysbus.h" > +#include "exec/memory.h" > +#include "net/net.h" > +#include "net/eth.h" > + > +#define TYPE_MSS_EMAC "msf2-emac" > +#define MSS_EMAC(obj) \ > + OBJECT_CHECK(MSF2EmacState, (obj), TYPE_MSS_EMAC) > + > +#define R_MAX (0x1a0 / 4) > +#define PHY_MAX_REGS 32 > + > +typedef struct MSF2EmacState { > + SysBusDevice parent; > + > + MemoryRegion mmio; > + MemoryRegion *dma_mr; > + AddressSpace dma_as; > + > + qemu_irq irq; > + NICState *nic; > + NICConf conf; > + > + uint8_t mac_addr[ETH_ALEN]; > + uint32_t rx_desc; > + uint16_t phy_regs[PHY_MAX_REGS]; > + > + uint32_t regs[R_MAX]; > +} MSF2EmacState; > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block 2020-04-15 6:13 ` Philippe Mathieu-Daudé @ 2020-04-15 10:59 ` sundeep subbaraya 0 siblings, 0 replies; 6+ messages in thread From: sundeep subbaraya @ 2020-04-15 10:59 UTC (permalink / raw) To: Philippe Mathieu-Daudé Cc: Peter Maydell, Jason Wang, qemu-arm, Philippe Mathieu-Daudé, QEMU Developers Hi Philippe, On Wed, Apr 15, 2020 at 11:43 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > On 4/14/20 5:02 PM, sundeep.lkml@gmail.com wrote: > > From: Subbaraya Sundeep <sundeep.lkml@gmail.com> > > > > Modelled Ethernet MAC of Smartfusion2 SoC. > > Micrel KSZ8051 PHY is present on Emcraft's > > SOM kit hence same PHY is emulated. > > > > Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> > > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > > --- > > MAINTAINERS | 2 + > > hw/net/Makefile.objs | 1 + > > hw/net/msf2-emac.c | 566 +++++++++++++++++++++++++++++++++++++++++++++ > > include/hw/net/msf2-emac.h | 53 +++++ > > 4 files changed, 622 insertions(+) > > create mode 100644 hw/net/msf2-emac.c > > create mode 100644 include/hw/net/msf2-emac.h > > > > diff --git a/MAINTAINERS b/MAINTAINERS > > index 642c8e0..9d0ff20 100644 > > --- a/MAINTAINERS > > +++ b/MAINTAINERS > > @@ -919,6 +919,8 @@ F: include/hw/arm/msf2-soc.h > > F: include/hw/misc/msf2-sysreg.h > > F: include/hw/timer/mss-timer.h > > F: include/hw/ssi/mss-spi.h > > +F: hw/net/msf2-emac.c > > +F: include/hw/net/msf2-emac.h > > > > Emcraft M2S-FG484 > > M: Subbaraya Sundeep <sundeep.lkml@gmail.com> > > diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs > > index af4d194..f2b7398 100644 > > --- a/hw/net/Makefile.objs > > +++ b/hw/net/Makefile.objs > > @@ -55,3 +55,4 @@ common-obj-$(CONFIG_ROCKER) += rocker/rocker.o rocker/rocker_fp.o \ > > obj-$(call lnot,$(CONFIG_ROCKER)) += rocker/qmp-norocker.o > > > > common-obj-$(CONFIG_CAN_BUS) += can/ > > +common-obj-$(CONFIG_MSF2) += msf2-emac.o > > diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c > > new file mode 100644 > > index 0000000..cae40fd > > --- /dev/null > > +++ b/hw/net/msf2-emac.c > > @@ -0,0 +1,566 @@ > > +/* > > + * QEMU model of the Smartfusion2 Ethernet MAC. > > + * > > + * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>. > > + * > > + * Permission is hereby granted, free of charge, to any person obtaining a copy > > + * of this software and associated documentation files (the "Software"), to deal > > + * in the Software without restriction, including without limitation the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > > + * THE SOFTWARE. > > + * > > + * Refer to section Ethernet MAC in the document: > > + * UG0331: SmartFusion2 Microcontroller Subsystem User Guide > > + * Datasheet URL: > > + * https://www.microsemi.com/document-portal/cat_view/56661-internal-documents/ > > + * 56758-soc?lang=en&limit=20&limitstart=220 > > + */ > > + > > +#include "qemu/osdep.h" > > +#include "qemu-common.h" > > +#include "qemu/log.h" > > +#include "qapi/error.h" > > +#include "exec/address-spaces.h" > > +#include "hw/registerfields.h" > > +#include "hw/net/msf2-emac.h" > > +#include "hw/net/mii.h" > > +#include "hw/irq.h" > > +#include "hw/qdev-properties.h" > > +#include "migration/vmstate.h" > > + > > +REG32(CFG1, 0x0) > > + FIELD(CFG1, RESET, 31, 1) > > + FIELD(CFG1, RX_EN, 2, 1) > > + FIELD(CFG1, TX_EN, 0, 1) > > + FIELD(CFG1, LB_EN, 8, 1) > > +REG32(CFG2, 0x4) > > +REG32(IFG, 0x8) > > +REG32(HALF_DUPLEX, 0xc) > > +REG32(MAX_FRAME_LENGTH, 0x10) > > +REG32(MII_CMD, 0x24) > > + FIELD(MII_CMD, READ, 0, 1) > > +REG32(MII_ADDR, 0x28) > > + FIELD(MII_ADDR, REGADDR, 0, 5) > > + FIELD(MII_ADDR, PHYADDR, 8, 5) > > +REG32(MII_CTL, 0x2c) > > +REG32(MII_STS, 0x30) > > +REG32(STA1, 0x40) > > +REG32(STA2, 0x44) > > +REG32(FIFO_CFG0, 0x48) > > +REG32(DMA_TX_CTL, 0x180) > > + FIELD(DMA_TX_CTL, EN, 0, 1) > > +REG32(DMA_TX_DESC, 0x184) > > +REG32(DMA_TX_STATUS, 0x188) > > + FIELD(DMA_TX_STATUS, PKTCNT, 16, 8) > > + FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1) > > + FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1) > > +REG32(DMA_RX_CTL, 0x18c) > > + FIELD(DMA_RX_CTL, EN, 0, 1) > > +REG32(DMA_RX_DESC, 0x190) > > +REG32(DMA_RX_STATUS, 0x194) > > + FIELD(DMA_RX_STATUS, PKTCNT, 16, 8) > > + FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1) > > + FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1) > > +REG32(DMA_IRQ_MASK, 0x198) > > +REG32(DMA_IRQ, 0x19c) > > + > > +#define EMPTY_MASK (1 << 31) > > +#define PKT_SIZE 0x7FF > > +#define PHYADDR 0x1 > > +#define MAX_PKT_SIZE 2048 > > + > > +typedef struct { > > + uint32_t pktaddr; > > + uint32_t pktsize; > > + uint32_t next; > > +} EmacDesc; > > + > > +static uint32_t emac_get_isr(MSF2EmacState *s) > > +{ > > + uint32_t ier = s->regs[R_DMA_IRQ_MASK]; > > + uint32_t tx = s->regs[R_DMA_TX_STATUS] & 0xF; > > + uint32_t rx = s->regs[R_DMA_RX_STATUS] & 0xF; > > + uint32_t isr = (rx << 4) | tx; > > + > > + s->regs[R_DMA_IRQ] = ier & isr; > > + return s->regs[R_DMA_IRQ]; > > +} > > + > > +static void emac_update_irq(MSF2EmacState *s) > > +{ > > + bool intr = emac_get_isr(s); > > + > > + qemu_set_irq(s->irq, intr); > > +} > > + > > +static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) > > +{ > > + address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); > > + /* Convert from LE into host endianness. */ > > + d->pktaddr = le32_to_cpu(d->pktaddr); > > + d->pktsize = le32_to_cpu(d->pktsize); > > + d->next = le32_to_cpu(d->next); > > +} > > + > > +static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) > > +{ > > + /* Convert from host endianness into LE. */ > > + d->pktaddr = cpu_to_le32(d->pktaddr); > > + d->pktsize = cpu_to_le32(d->pktsize); > > + d->next = cpu_to_le32(d->next); > > + > > + address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof *d); > > +} > > + > > +static void msf2_dma_tx(MSF2EmacState *s) > > +{ > > + NetClientState *nc = qemu_get_queue(s->nic); > > + hwaddr desc = s->regs[R_DMA_TX_DESC]; > > + uint8_t buf[MAX_PKT_SIZE]; > > + EmacDesc d; > > + int size; > > + uint8_t pktcnt; > > + uint32_t status; > > + > > + if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) { > > + return; > > + } > > + > > + while (1) { > > + emac_load_desc(s, &d, desc); > > + if (d.pktsize & EMPTY_MASK) { > > + break; > > + } > > + size = d.pktsize & PKT_SIZE; > > + address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, > > + buf, size); > > + /* > > + * This is very basic way to send packets. Ideally there should be > > + * a FIFO and packets should be sent out from FIFO only when > > + * R_CFG1 bit 0 is set. > > + */ > > + if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) { > > + nc->info->receive(nc, buf, size); > > + } else { > > + qemu_send_packet(nc, buf, size); > > + } > > + d.pktsize |= EMPTY_MASK; > > + emac_store_desc(s, &d, desc); > > + /* update sent packets count */ > > + status = s->regs[R_DMA_TX_STATUS]; > > + pktcnt = FIELD_EX32(status, DMA_TX_STATUS, PKTCNT); > > + pktcnt++; > > + s->regs[R_DMA_TX_STATUS] = FIELD_DP32(status, DMA_TX_STATUS, > > + PKTCNT, pktcnt); > > + s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_PKT_SENT_MASK; > > + desc = d.next; > > + } > > + s->regs[R_DMA_TX_STATUS] |= R_DMA_TX_STATUS_UNDERRUN_MASK; > > + s->regs[R_DMA_TX_CTL] &= ~R_DMA_TX_CTL_EN_MASK; > > +} > > + > > +static void msf2_phy_update_link(MSF2EmacState *s) > > +{ > > + /* Autonegotiation status mirrors link status. */ > > + if (qemu_get_queue(s->nic)->link_down) { > > + s->phy_regs[MII_BMSR] &= ~(MII_BMSR_AN_COMP | > > + MII_BMSR_LINK_ST); > > + } else { > > + s->phy_regs[MII_BMSR] |= (MII_BMSR_AN_COMP | > > + MII_BMSR_LINK_ST); > > + } > > +} > > + > > +static void msf2_phy_reset(MSF2EmacState *s) > > +{ > > + memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); > > + s->phy_regs[MII_BMCR] = 0x1140; > > + s->phy_regs[MII_BMSR] = 0x7968; > > + s->phy_regs[MII_PHYID1] = 0x0022; > > + s->phy_regs[MII_PHYID2] = 0x1550; > > + s->phy_regs[MII_ANAR] = 0x01E1; > > + s->phy_regs[MII_ANLPAR] = 0xCDE1; > > + > > + msf2_phy_update_link(s); > > +} > > + > > +static void write_to_phy(MSF2EmacState *s) > > +{ > > + uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; > > + uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & > > + R_MII_ADDR_REGADDR_MASK; > > + uint16_t data = s->regs[R_MII_CTL] & 0xFFFF; > > + > > + if (phy_addr != PHYADDR) { > > + return; > > + } > > + > > + switch (reg_addr) { > > + case MII_BMCR: > > + if (data & MII_BMCR_RESET) { > > + /* Phy reset */ > > + msf2_phy_reset(s); > > + data &= ~MII_BMCR_RESET; > > + } > > + if (data & MII_BMCR_AUTOEN) { > > + /* Complete autonegotiation immediately */ > > + data &= ~MII_BMCR_AUTOEN; > > + s->phy_regs[MII_BMSR] |= MII_BMSR_AN_COMP; > > + } > > + break; > > + } > > + > > + s->phy_regs[reg_addr] = data; > > +} > > + > > +static uint16_t read_from_phy(MSF2EmacState *s) > > +{ > > + uint8_t reg_addr = s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; > > + uint8_t phy_addr = (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT) & > > + R_MII_ADDR_REGADDR_MASK; > > + > > + if (phy_addr == PHYADDR) { > > + return s->phy_regs[reg_addr]; > > + } else { > > + return 0xFFFF; > > + } > > +} > > + > > +static void msf2_emac_do_reset(MSF2EmacState *s) > > +{ > > + memset(&s->regs[0], 0, sizeof(s->regs)); > > + s->regs[R_CFG1] = 0x80000000; > > + s->regs[R_CFG2] = 0x00007000; > > + s->regs[R_IFG] = 0x40605060; > > + s->regs[R_HALF_DUPLEX] = 0x00A1F037; > > + s->regs[R_MAX_FRAME_LENGTH] = 0x00000600; > > + > > + msf2_phy_reset(s); > > +} > > + > > +static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size) > > +{ > > + MSF2EmacState *s = opaque; > > + uint32_t r = 0; > > + > > + addr >>= 2; > > + > > + switch (addr) { > > + case R_DMA_IRQ: > > + r = emac_get_isr(s); > > + break; > > + default: > > + if (addr >= ARRAY_SIZE(s->regs)) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, > > + addr * 4); > > + return r; > > + } > > + r = s->regs[addr]; > > + break; > > + } > > + return r; > > +} > > + > > +static void emac_write(void *opaque, hwaddr addr, uint64_t val64, > > + unsigned int size) > > +{ > > + MSF2EmacState *s = opaque; > > + uint32_t value = val64; > > + uint32_t enreqbits; > > + uint8_t pktcnt; > > + > > + addr >>= 2; > > + switch (addr) { > > + case R_DMA_TX_CTL: > > + s->regs[addr] = value; > > + if (value & R_DMA_TX_CTL_EN_MASK) { > > + msf2_dma_tx(s); > > + } > > + break; > > + case R_DMA_RX_CTL: > > + s->regs[addr] = value; > > + if (value & R_DMA_RX_CTL_EN_MASK) { > > + s->rx_desc = s->regs[R_DMA_RX_DESC]; > > + qemu_flush_queued_packets(qemu_get_queue(s->nic)); > > + } > > + break; > > + case R_CFG1: > > + if (value & R_CFG1_RESET_MASK) { > > + msf2_emac_do_reset(s); > > + } > > Missing break? Yes. thanks for catching. > > > + case R_FIFO_CFG0: > > + /* > > + * For our implementation, turning on modules is instantaneous, > > + * so the states requested via the *ENREQ bits appear in the > > + * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC > > + * module are not emulated here since it deals with start of frames, > > + * inter-packet gap and control frames. > > + */ > > + enreqbits = extract32(value, 8, 5); > > + s->regs[addr] = deposit32(value, 16, 5, enreqbits); > > + break; > > + case R_DMA_TX_DESC: > > + if (value & 0x3) { > > + qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should be" > > + " 32 bit aligned\n"); > > + } > > + /* Ignore [1:0] bits */ > > + s->regs[addr] = value & ~3; > > + break; > > + case R_DMA_RX_DESC: > > + if (value & 0x3) { > > + qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should be" > > + " 32 bit aligned\n"); > > + } > > + /* Ignore [1:0] bits */ > > + s->regs[addr] = value & ~3; > > + break; > > + case R_DMA_TX_STATUS: > > + if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) { > > + s->regs[addr] &= ~R_DMA_TX_STATUS_UNDERRUN_MASK; > > + } > > + if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) { > > + pktcnt = FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT); > > + pktcnt--; > > + s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_TX_STATUS, > > + PKTCNT, pktcnt); > > + if (pktcnt == 0) { > > + s->regs[addr] &= ~R_DMA_TX_STATUS_PKT_SENT_MASK; > > + } > > + } > > + break; > > + case R_DMA_RX_STATUS: > > + if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) { > > + s->regs[addr] &= ~R_DMA_RX_STATUS_OVERFLOW_MASK; > > + } > > + if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) { > > + pktcnt = FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT); > > + pktcnt--; > > + s->regs[addr] = FIELD_DP32(s->regs[addr], DMA_RX_STATUS, > > + PKTCNT, pktcnt); > > + if (pktcnt == 0) { > > + s->regs[addr] &= ~R_DMA_RX_STATUS_PKT_RCVD_MASK; > > + } > > + } > > + break; > > + case R_DMA_IRQ: > > + break; > > + case R_MII_CMD: > > + if (value & R_MII_CMD_READ_MASK) { > > + s->regs[R_MII_STS] = read_from_phy(s); > > + } > > + break; > > + case R_MII_CTL: > > + s->regs[addr] = value; > > + write_to_phy(s); > > + break; > > + case R_STA1: > > + s->regs[addr] = value; > > + /* > > + * R_STA1 [31:24] : octet 1 of mac address > > + * R_STA1 [23:16] : octet 2 of mac address > > + * R_STA1 [15:8] : octet 3 of mac address > > + * R_STA1 [7:0] : octet 4 of mac address > > + */ > > + stl_le_p(s->mac_addr, value); > > + break; > > + case R_STA2: > > + s->regs[addr] = value; > > + /* > > + * R_STA2 [31:24] : octet 5 of mac address > > + * R_STA2 [23:16] : octet 6 of mac address > > + */ > > + stw_le_p(s->mac_addr + 4, value >> 16); > > + break; > > + default: > > + if (addr >= ARRAY_SIZE(s->regs)) { > > + qemu_log_mask(LOG_GUEST_ERROR, > > + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, > > + addr * 4); > > + return; > > + } > > + s->regs[addr] = value; > > + break; > > + } > > + emac_update_irq(s); > > +} > > + > > +static const MemoryRegionOps emac_ops = { > > + .read = emac_read, > > + .write = emac_write, > > + .endianness = DEVICE_NATIVE_ENDIAN, > > + .impl = { > > + .min_access_size = 4, > > + .max_access_size = 4 > > + } > > +}; > > + > > +static bool emac_can_rx(NetClientState *nc) > > +{ > > + MSF2EmacState *s = qemu_get_nic_opaque(nc); > > + > > + return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) && > > + (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK); > > +} > > + > > +static bool match_addr(MSF2EmacState *s, const uint8_t *buf) > > +{ > > + /* The broadcast MAC address: FF:FF:FF:FF:FF:FF */ > > + static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, > > + 0xFF, 0xFF }; > > + > > + if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) { > > + return true; > > + } > > + > > + if (!memcmp(buf, s->mac_addr, sizeof(s->mac_addr))) { > > + return false; > > + } > > + > > + return true; > > Yes, or: > > return !!memcmp(buf, s->mac_addr, sizeof(s->mac_addr)); > This logic is wrong and unicast filter always fail and returns true for all packets. Need to use stl_be_p instead of stl_le_p. buf[0]:0xc0, 0xb1 0x3c 0x83 0x83 0x83 mac[0]:0x83, 0x3c 0xb1 0xc0 0x83 0x83 I will fix this and send another version. Thanks, Sundeep > > +} > > + > > +static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size) > > +{ > > + MSF2EmacState *s = qemu_get_nic_opaque(nc); > > + EmacDesc d; > > + uint8_t pktcnt; > > + uint32_t status; > > + > > + if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) { > > + return size; > > + } > > + if (!match_addr(s, buf)) { > > + return size; > > + } > > + > > + emac_load_desc(s, &d, s->rx_desc); > > + > > + if (d.pktsize & EMPTY_MASK) { > > + address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, > > + buf, size & PKT_SIZE); > > + d.pktsize = size & PKT_SIZE; > > + emac_store_desc(s, &d, s->rx_desc); > > + /* update received packets count */ > > + status = s->regs[R_DMA_RX_STATUS]; > > + pktcnt = FIELD_EX32(status, DMA_RX_STATUS, PKTCNT); > > + pktcnt++; > > + s->regs[R_DMA_RX_STATUS] = FIELD_DP32(status, DMA_RX_STATUS, > > + PKTCNT, pktcnt); > > + s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_PKT_RCVD_MASK; > > + s->rx_desc = d.next; > > + } else { > > + s->regs[R_DMA_RX_CTL] &= ~R_DMA_RX_CTL_EN_MASK; > > + s->regs[R_DMA_RX_STATUS] |= R_DMA_RX_STATUS_OVERFLOW_MASK; > > + } > > + emac_update_irq(s); > > + return size; > > +} > > + > > +static void msf2_emac_reset(DeviceState *dev) > > +{ > > + MSF2EmacState *s = MSS_EMAC(dev); > > + > > + msf2_emac_do_reset(s); > > +} > > + > > +static void emac_set_link(NetClientState *nc) > > +{ > > + MSF2EmacState *s = qemu_get_nic_opaque(nc); > > + > > + msf2_phy_update_link(s); > > +} > > + > > +static NetClientInfo net_msf2_emac_info = { > > + .type = NET_CLIENT_DRIVER_NIC, > > + .size = sizeof(NICState), > > + .can_receive = emac_can_rx, > > + .receive = emac_rx, > > + .link_status_changed = emac_set_link, > > +}; > > + > > +static void msf2_emac_realize(DeviceState *dev, Error **errp) > > +{ > > + MSF2EmacState *s = MSS_EMAC(dev); > > + > > + if (!s->dma_mr) { > > + error_setg(errp, "MSS_EMAC 'ahb-bus' link not set"); > > + return; > > + } > > + > > + address_space_init(&s->dma_as, s->dma_mr, "emac-ahb"); > > + > > + qemu_macaddr_default_if_unset(&s->conf.macaddr); > > + s->nic = qemu_new_nic(&net_msf2_emac_info, &s->conf, > > + object_get_typename(OBJECT(dev)), dev->id, s); > > + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); > > +} > > + > > +static void msf2_emac_init(Object *obj) > > +{ > > + MSF2EmacState *s = MSS_EMAC(obj); > > + > > + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); > > + > > + memory_region_init_io(&s->mmio, obj, &emac_ops, s, > > + "msf2-emac", R_MAX * 4); > > + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); > > +} > > + > > +static Property msf2_emac_properties[] = { > > + DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr, > > + TYPE_MEMORY_REGION, MemoryRegion *), > > + DEFINE_NIC_PROPERTIES(MSF2EmacState, conf), > > + DEFINE_PROP_END_OF_LIST(), > > +}; > > + > > +static const VMStateDescription vmstate_msf2_emac = { > > + .name = TYPE_MSS_EMAC, > > + .version_id = 1, > > + .minimum_version_id = 1, > > + .fields = (VMStateField[]) { > > + VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN), > > + VMSTATE_UINT32(rx_desc, MSF2EmacState), > > + VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS), > > + VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX), > > + VMSTATE_END_OF_LIST() > > + } > > +}; > > + > > +static void msf2_emac_class_init(ObjectClass *klass, void *data) > > +{ > > + DeviceClass *dc = DEVICE_CLASS(klass); > > + > > + dc->realize = msf2_emac_realize; > > + dc->reset = msf2_emac_reset; > > + dc->vmsd = &vmstate_msf2_emac; > > + device_class_set_props(dc, msf2_emac_properties); > > +} > > + > > +static const TypeInfo msf2_emac_info = { > > + .name = TYPE_MSS_EMAC, > > + .parent = TYPE_SYS_BUS_DEVICE, > > + .instance_size = sizeof(MSF2EmacState), > > + .instance_init = msf2_emac_init, > > + .class_init = msf2_emac_class_init, > > +}; > > + > > +static void msf2_emac_register_types(void) > > +{ > > + type_register_static(&msf2_emac_info); > > +} > > + > > +type_init(msf2_emac_register_types) > > diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h > > new file mode 100644 > > index 0000000..37966d3 > > --- /dev/null > > +++ b/include/hw/net/msf2-emac.h > > @@ -0,0 +1,53 @@ > > +/* > > + * QEMU model of the Smartfusion2 Ethernet MAC. > > + * > > + * Copyright (c) 2020 Subbaraya Sundeep <sundeep.lkml@gmail.com>. > > + * > > + * Permission is hereby granted, free of charge, to any person obtaining a copy > > + * of this software and associated documentation files (the "Software"), to deal > > + * in the Software without restriction, including without limitation the rights > > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > > + * copies of the Software, and to permit persons to whom the Software is > > + * furnished to do so, subject to the following conditions: > > + * > > + * The above copyright notice and this permission notice shall be included in > > + * all copies or substantial portions of the Software. > > + * > > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > > + * THE SOFTWARE. > > + */ > > + > > +#include "hw/sysbus.h" > > +#include "exec/memory.h" > > +#include "net/net.h" > > +#include "net/eth.h" > > + > > +#define TYPE_MSS_EMAC "msf2-emac" > > +#define MSS_EMAC(obj) \ > > + OBJECT_CHECK(MSF2EmacState, (obj), TYPE_MSS_EMAC) > > + > > +#define R_MAX (0x1a0 / 4) > > +#define PHY_MAX_REGS 32 > > + > > +typedef struct MSF2EmacState { > > + SysBusDevice parent; > > + > > + MemoryRegion mmio; > > + MemoryRegion *dma_mr; > > + AddressSpace dma_as; > > + > > + qemu_irq irq; > > + NICState *nic; > > + NICConf conf; > > + > > + uint8_t mac_addr[ETH_ALEN]; > > + uint32_t rx_desc; > > + uint16_t phy_regs[PHY_MAX_REGS]; > > + > > + uint32_t regs[R_MAX]; > > +} MSF2EmacState; > > ^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu devel PATCH v5 2/3] msf2: Add EMAC block to SmartFusion2 SoC 2020-04-14 15:02 [Qemu devel PATCH v5 0/3] Add SmartFusion2 EMAC block sundeep.lkml 2020-04-14 15:02 ` [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block sundeep.lkml @ 2020-04-14 15:02 ` sundeep.lkml 2020-04-14 15:02 ` [Qemu devel PATCH v5 3/3] tests/boot_linux_console: Add ethernet test to SmartFusion2 sundeep.lkml 2 siblings, 0 replies; 6+ messages in thread From: sundeep.lkml @ 2020-04-14 15:02 UTC (permalink / raw) To: jasowang, peter.maydell, philmd, qemu-devel, qemu-arm; +Cc: Subbaraya Sundeep From: Subbaraya Sundeep <sundeep.lkml@gmail.com> With SmartFusion2 Ethernet MAC model in place this patch adds the same to SoC. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- hw/arm/msf2-soc.c | 26 ++++++++++++++++++++++++-- include/hw/arm/msf2-soc.h | 2 ++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 588d643..a455b88 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -1,7 +1,7 @@ /* * SmartFusion2 SoC emulation. * - * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com> + * Copyright (c) 2017-2020 Subbaraya Sundeep <sundeep.lkml@gmail.com> * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -35,11 +35,14 @@ #define MSF2_TIMER_BASE 0x40004000 #define MSF2_SYSREG_BASE 0x40038000 +#define MSF2_EMAC_BASE 0x40041000 #define ENVM_BASE_ADDRESS 0x60000000 #define SRAM_BASE_ADDRESS 0x20000000 +#define MSF2_EMAC_IRQ 12 + #define MSF2_ENVM_MAX_SIZE (512 * KiB) /* @@ -81,6 +84,13 @@ static void m2sxxx_soc_initfn(Object *obj) sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), TYPE_MSS_SPI); } + + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), + TYPE_MSS_EMAC); + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC); + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); + } } static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) @@ -192,6 +202,19 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) g_free(bus_name); } + dev = DEVICE(&s->emac); + object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()), + "ahb-bus", &error_abort); + object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); + if (err != NULL) { + error_propagate(errp, err); + return; + } + busdev = SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ)); + /* Below devices are not modelled yet. */ create_unimplemented_device("i2c_0", 0x40002000, 0x1000); create_unimplemented_device("dma", 0x40003000, 0x1000); @@ -202,7 +225,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) create_unimplemented_device("can", 0x40015000, 0x1000); create_unimplemented_device("rtc", 0x40017000, 0x1000); create_unimplemented_device("apb_config", 0x40020000, 0x10000); - create_unimplemented_device("emac", 0x40041000, 0x1000); create_unimplemented_device("usb", 0x40043000, 0x1000); } diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index 3cfe5c7..c9cb214 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -29,6 +29,7 @@ #include "hw/timer/mss-timer.h" #include "hw/misc/msf2-sysreg.h" #include "hw/ssi/mss-spi.h" +#include "hw/net/msf2-emac.h" #define TYPE_MSF2_SOC "msf2-soc" #define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) @@ -62,6 +63,7 @@ typedef struct MSF2State { MSF2SysregState sysreg; MSSTimerState timer; MSSSpiState spi[MSF2_NUM_SPIS]; + MSF2EmacState emac; } MSF2State; #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu devel PATCH v5 3/3] tests/boot_linux_console: Add ethernet test to SmartFusion2 2020-04-14 15:02 [Qemu devel PATCH v5 0/3] Add SmartFusion2 EMAC block sundeep.lkml 2020-04-14 15:02 ` [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block sundeep.lkml 2020-04-14 15:02 ` [Qemu devel PATCH v5 2/3] msf2: Add EMAC block to SmartFusion2 SoC sundeep.lkml @ 2020-04-14 15:02 ` sundeep.lkml 2 siblings, 0 replies; 6+ messages in thread From: sundeep.lkml @ 2020-04-14 15:02 UTC (permalink / raw) To: jasowang, peter.maydell, philmd, qemu-devel, qemu-arm; +Cc: Subbaraya Sundeep From: Subbaraya Sundeep <sundeep.lkml@gmail.com> In addition to simple serial test this patch uses ping to test the ethernet block modelled in SmartFusion2 SoC. Signed-off-by: Subbaraya Sundeep <sundeep.lkml@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- tests/acceptance/boot_linux_console.py | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index f825cd9..c6b06a1 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -336,13 +336,13 @@ class BootLinuxConsole(Test): """ uboot_url = ('https://raw.githubusercontent.com/' 'Subbaraya-Sundeep/qemu-test-binaries/' - 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/u-boot') - uboot_hash = 'abba5d9c24cdd2d49cdc2a8aa92976cf20737eff' + 'fe371d32e50ca682391e1e70ab98c2942aeffb01/u-boot') + uboot_hash = 'cbb8cbab970f594bf6523b9855be209c08374ae2' uboot_path = self.fetch_asset(uboot_url, asset_hash=uboot_hash) spi_url = ('https://raw.githubusercontent.com/' 'Subbaraya-Sundeep/qemu-test-binaries/' - 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/spi.bin') - spi_hash = '85f698329d38de63aea6e884a86fbde70890a78a' + 'fe371d32e50ca682391e1e70ab98c2942aeffb01/spi.bin') + spi_hash = '65523a1835949b6f4553be96dec1b6a38fb05501' spi_path = self.fetch_asset(spi_url, asset_hash=spi_hash) self.vm.set_console() @@ -352,7 +352,12 @@ class BootLinuxConsole(Test): '-drive', 'file=' + spi_path + ',if=mtd,format=raw', '-no-reboot') self.vm.launch() - self.wait_for_console_pattern('init started: BusyBox') + self.wait_for_console_pattern('Enter \'help\' for a list') + + exec_command_and_wait_for_pattern(self, 'ifconfig eth0 10.0.2.15', + 'eth0: link becomes ready') + exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2', + '3 packets transmitted, 3 packets received, 0% packet loss') def do_test_arm_raspi2(self, uart_id): """ -- 2.7.4 ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-04-15 11:00 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-04-14 15:02 [Qemu devel PATCH v5 0/3] Add SmartFusion2 EMAC block sundeep.lkml 2020-04-14 15:02 ` [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block sundeep.lkml 2020-04-15 6:13 ` Philippe Mathieu-Daudé 2020-04-15 10:59 ` sundeep subbaraya 2020-04-14 15:02 ` [Qemu devel PATCH v5 2/3] msf2: Add EMAC block to SmartFusion2 SoC sundeep.lkml 2020-04-14 15:02 ` [Qemu devel PATCH v5 3/3] tests/boot_linux_console: Add ethernet test to SmartFusion2 sundeep.lkml
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).