From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Tong Ho" <tong.ho@xilinx.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 05/10] net: cadence_gem: Set ISR according to queue in use
Date: Sat, 2 May 2020 23:23:09 +0530 [thread overview]
Message-ID: <1588441994-21447-6-git-send-email-sai.pavan.boddu@xilinx.com> (raw)
In-Reply-To: <1588441994-21447-1-git-send-email-sai.pavan.boddu@xilinx.com>
Set ISR according to queue in use, added interrupt support for
all queues.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
hw/net/cadence_gem.c | 31 ++++++++++++++++++++++---------
1 file changed, 22 insertions(+), 9 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index e745d60..cc9e735 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -896,7 +896,13 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
- s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
+ if (q == 0) {
+ s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
+ } else {
+ s->regs[GEM_INT_Q1_STATUS + q - 1] |= GEM_INT_RXUSED &
+ ~(s->regs[GEM_INT_Q1_MASK + q - 1]);
+ }
+
/* Handle interrupt consequences */
gem_update_int_status(s);
}
@@ -1070,8 +1076,12 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
gem_receive_updatestats(s, buf, size);
s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
- s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
-
+ if (q == 0) {
+ s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
+ } else {
+ s->regs[GEM_INT_Q1_STATUS + q - 1] |= GEM_INT_RXCMPL &
+ ~(s->regs[GEM_INT_Q1_MASK + q - 1]);
+ }
/* Handle interrupt consequences */
gem_update_int_status(s);
@@ -1222,12 +1232,12 @@ static void gem_transmit(CadenceGEMState *s)
DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
- s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
-
+ if (q == 0) {
+ s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
+ } else {
/* Update queue interrupt status */
- if (s->num_priority_queues > 1) {
- s->regs[GEM_INT_Q1_STATUS + q] |=
- GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
+ s->regs[GEM_INT_Q1_STATUS + q - 1] |=
+ GEM_INT_TXCMPL & ~s->regs[GEM_INT_Q1_MASK + q - 1];
}
/* Handle interrupt consequences */
@@ -1279,7 +1289,10 @@ static void gem_transmit(CadenceGEMState *s)
if (tx_desc_get_used(desc)) {
s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
- s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
+ /* IRQ TXUSED is defined only for queue 0 */
+ if (q == 0) {
+ s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
+ }
gem_update_int_status(s);
}
}
--
2.7.4
next prev parent reply other threads:[~2020-05-02 18:07 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-02 17:53 [PATCH 00/10] Cadence GEM Fixes Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 01/10] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 02/10] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 03/10] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 04/10] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-02 17:53 ` Sai Pavan Boddu [this message]
2020-05-02 17:53 ` [PATCH 06/10] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 08/10] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 09/10] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 10/10] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-02 19:08 ` [PATCH 00/10] Cadence GEM Fixes no-reply
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