From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Tong Ho" <tong.ho@xilinx.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH 08/10] net: cadence_gem: Update the reset value for interrupt mask register
Date: Sat, 2 May 2020 23:23:12 +0530 [thread overview]
Message-ID: <1588441994-21447-9-git-send-email-sai.pavan.boddu@xilinx.com> (raw)
In-Reply-To: <1588441994-21447-1-git-send-email-sai.pavan.boddu@xilinx.com>
Mask all interrupt on reset.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
hw/net/cadence_gem.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index e6a3d6c..68df92d 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1347,6 +1347,7 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_DESCONF2] = 0x2ab12800;
s->regs[GEM_DESCONF5] = 0x002f2045;
s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
+ s->regs[GEM_INT_Q1_MASK] = 0x00000CE6;
if (s->num_priority_queues > 1) {
queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
--
2.7.4
next prev parent reply other threads:[~2020-05-02 18:05 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-02 17:53 [PATCH 00/10] Cadence GEM Fixes Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 01/10] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 02/10] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 03/10] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 04/10] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 05/10] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 06/10] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-02 17:53 ` Sai Pavan Boddu [this message]
2020-05-02 17:53 ` [PATCH 09/10] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-02 17:53 ` [PATCH 10/10] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-02 19:08 ` [PATCH 00/10] Cadence GEM Fixes no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1588441994-21447-9-git-send-email-sai.pavan.boddu@xilinx.com \
--to=sai.pavan.boddu@xilinx.com \
--cc=Alistair.Francis@wdc.com \
--cc=armbru@redhat.com \
--cc=edgar.iglesias@gmail.com \
--cc=jasowang@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=philmd@redhat.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=rfried.dev@gmail.com \
--cc=tong.ho@xilinx.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).