From: Huacai Chen <chenhc@lemote.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: kvm@vger.kernel.org, "Huacai Chen" <chenhuacai@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
qemu-devel@nongnu.org,
"Aleksandar Markovic" <aleksandar.qemu.devel@gmail.com>,
"Fuxin Zhang" <zhangfx@lemote.com>,
"Huacai Chen" <chenhc@lemote.com>,
linux-mips@vger.kernel.org
Subject: [PATCH V3 06/14] KVM: MIPS: Introduce and use cpu_guest_has_ldpte
Date: Sun, 3 May 2020 18:05:59 +0800 [thread overview]
Message-ID: <1588500367-1056-7-git-send-email-chenhc@lemote.com> (raw)
In-Reply-To: <1588500367-1056-1-git-send-email-chenhc@lemote.com>
Loongson-3 has lddir/ldpte instructions and their related CP0 registers
are the same as HTW. So we introduce a cpu_guest_has_ldpte flag and use
it to indicate whether we need to save/restore HTW related CP0 registers
(PWBase, PWSize, PWField and PWCtl).
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/cpu-features.h | 3 +++
arch/mips/kernel/cpu-probe.c | 1 +
arch/mips/kvm/vz.c | 26 +++++++++++++-------------
3 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 400b123..e127495 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -659,6 +659,9 @@
#ifndef cpu_guest_has_htw
#define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW)
#endif
+#ifndef cpu_guest_has_ldpte
+#define cpu_guest_has_ldpte (cpu_data[0].guest.options & MIPS_CPU_LDPTE)
+#endif
#ifndef cpu_guest_has_mvh
#define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH)
#endif
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index ca2e6f1..be1b556 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -2004,6 +2004,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
* register, we correct it here.
*/
c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
+ c->guest.options |= MIPS_CPU_LDPTE;
c->writecombine = _CACHE_UNCACHED_ACCELERATED;
c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c
index 17932ab..422cd06 100644
--- a/arch/mips/kvm/vz.c
+++ b/arch/mips/kvm/vz.c
@@ -1706,7 +1706,7 @@ static unsigned long kvm_vz_num_regs(struct kvm_vcpu *vcpu)
ret += ARRAY_SIZE(kvm_vz_get_one_regs_contextconfig);
if (cpu_guest_has_segments)
ret += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
- if (cpu_guest_has_htw)
+ if (cpu_guest_has_htw || cpu_guest_has_ldpte)
ret += ARRAY_SIZE(kvm_vz_get_one_regs_htw);
if (cpu_guest_has_maar && !cpu_guest_has_dyn_maar)
ret += 1 + ARRAY_SIZE(vcpu->arch.maar);
@@ -1755,7 +1755,7 @@ static int kvm_vz_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
return -EFAULT;
indices += ARRAY_SIZE(kvm_vz_get_one_regs_segments);
}
- if (cpu_guest_has_htw) {
+ if (cpu_guest_has_htw || cpu_guest_has_ldpte) {
if (copy_to_user(indices, kvm_vz_get_one_regs_htw,
sizeof(kvm_vz_get_one_regs_htw)))
return -EFAULT;
@@ -1878,17 +1878,17 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
*v = read_gc0_segctl2();
break;
case KVM_REG_MIPS_CP0_PWBASE:
- if (!cpu_guest_has_htw)
+ if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
*v = read_gc0_pwbase();
break;
case KVM_REG_MIPS_CP0_PWFIELD:
- if (!cpu_guest_has_htw)
+ if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
*v = read_gc0_pwfield();
break;
case KVM_REG_MIPS_CP0_PWSIZE:
- if (!cpu_guest_has_htw)
+ if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
*v = read_gc0_pwsize();
break;
@@ -1896,7 +1896,7 @@ static int kvm_vz_get_one_reg(struct kvm_vcpu *vcpu,
*v = (long)read_gc0_wired();
break;
case KVM_REG_MIPS_CP0_PWCTL:
- if (!cpu_guest_has_htw)
+ if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
*v = read_gc0_pwctl();
break;
@@ -2101,17 +2101,17 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
write_gc0_segctl2(v);
break;
case KVM_REG_MIPS_CP0_PWBASE:
- if (!cpu_guest_has_htw)
+ if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
write_gc0_pwbase(v);
break;
case KVM_REG_MIPS_CP0_PWFIELD:
- if (!cpu_guest_has_htw)
+ if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
write_gc0_pwfield(v);
break;
case KVM_REG_MIPS_CP0_PWSIZE:
- if (!cpu_guest_has_htw)
+ if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
write_gc0_pwsize(v);
break;
@@ -2119,7 +2119,7 @@ static int kvm_vz_set_one_reg(struct kvm_vcpu *vcpu,
change_gc0_wired(MIPSR6_WIRED_WIRED, v);
break;
case KVM_REG_MIPS_CP0_PWCTL:
- if (!cpu_guest_has_htw)
+ if (!cpu_guest_has_htw && !cpu_guest_has_ldpte)
return -EINVAL;
write_gc0_pwctl(v);
break;
@@ -2580,7 +2580,7 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
}
/* restore HTW registers */
- if (cpu_guest_has_htw) {
+ if (cpu_guest_has_htw || cpu_guest_has_ldpte) {
kvm_restore_gc0_pwbase(cop0);
kvm_restore_gc0_pwfield(cop0);
kvm_restore_gc0_pwsize(cop0);
@@ -2685,8 +2685,8 @@ static int kvm_vz_vcpu_put(struct kvm_vcpu *vcpu, int cpu)
}
/* save HTW registers if enabled in guest */
- if (cpu_guest_has_htw &&
- kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW) {
+ if (cpu_guest_has_ldpte || (cpu_guest_has_htw &&
+ kvm_read_sw_gc0_config3(cop0) & MIPS_CONF3_PW)) {
kvm_save_gc0_pwbase(cop0);
kvm_save_gc0_pwfield(cop0);
kvm_save_gc0_pwsize(cop0);
--
2.7.0
next prev parent reply other threads:[~2020-05-03 10:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-03 10:05 [PATCH V3 00/14] KVM: MIPS: Add Loongson-3 support (Host Side) Huacai Chen
2020-05-03 10:05 ` [PATCH V3 01/14] KVM: MIPS: Define KVM_ENTRYHI_ASID to cpu_asid_mask(&boot_cpu_data) Huacai Chen
2020-05-06 23:42 ` Sasha Levin
2020-05-07 12:10 ` Aleksandar Markovic
2020-05-08 10:05 ` Aleksandar Markovic
2020-05-03 10:05 ` [PATCH V3 02/14] KVM: MIPS: Fix VPN2_MASK definition for variable cpu_vmbits Huacai Chen
2020-05-08 10:14 ` Aleksandar Markovic
2020-05-03 10:05 ` [PATCH V3 03/14] KVM: MIPS: Increase KVM_MAX_VCPUS and KVM_USER_MEM_SLOTS to 16 Huacai Chen
2020-05-08 10:16 ` Aleksandar Markovic
2020-05-03 10:05 ` [PATCH V3 04/14] KVM: MIPS: Add EVENTFD support which is needed by VHOST Huacai Chen
2020-05-08 9:08 ` Aleksandar Markovic
2020-05-08 10:08 ` Aleksandar Markovic
2020-05-03 10:05 ` [PATCH V3 05/14] KVM: MIPS: Use lddir/ldpte instructions to lookup gpa_mm.pgd Huacai Chen
2020-05-08 10:46 ` Aleksandar Markovic
2020-05-03 10:05 ` Huacai Chen [this message]
2020-05-08 10:49 ` [PATCH V3 06/14] KVM: MIPS: Introduce and use cpu_guest_has_ldpte Aleksandar Markovic
2020-05-03 10:06 ` [PATCH V3 07/14] KVM: MIPS: Use root tlb to control guest's CCA for Loongson-3 Huacai Chen
2020-05-08 10:53 ` Aleksandar Markovic
2020-05-03 10:06 ` [PATCH V3 08/14] KVM: MIPS: Let indexed cacheops cause guest exit on Loongson-3 Huacai Chen
2020-05-08 10:55 ` Aleksandar Markovic
2020-05-03 10:06 ` [PATCH V3 09/14] KVM: MIPS: Add more types of virtual interrupts Huacai Chen
2020-05-08 11:47 ` Aleksandar Markovic
2020-05-03 10:06 ` [PATCH V3 10/14] KVM: MIPS: Add Loongson-3 Virtual IPI interrupt support Huacai Chen
2020-05-08 11:22 ` Aleksandar Markovic
2020-05-09 7:58 ` Huacai Chen
2020-05-03 10:06 ` [PATCH V3 11/14] KVM: MIPS: Add CPUCFG emulation for Loongson-3 Huacai Chen
2020-05-03 10:06 ` [PATCH V3 12/14] KVM: MIPS: Add CONFIG6 and DIAG registers emulation Huacai Chen
2020-05-03 10:06 ` [PATCH V3 13/14] KVM: MIPS: Add more MMIO load/store instructions emulation Huacai Chen
2020-05-08 11:46 ` Aleksandar Markovic
2020-05-03 10:06 ` [PATCH V3 14/14] KVM: MIPS: Enable KVM support for Loongson-3 Huacai Chen
2020-05-08 11:43 ` [PATCH V3 00/14] KVM: MIPS: Add Loongson-3 support (Host Side) Aleksandar Markovic
2020-05-09 4:32 ` Huacai Chen
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