From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Tong Ho" <tong.ho@xilinx.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v2 06/10] net: cadence_gem: Add support for jumbo frames
Date: Mon, 4 May 2020 19:36:04 +0530 [thread overview]
Message-ID: <1588601168-27576-7-git-send-email-sai.pavan.boddu@xilinx.com> (raw)
In-Reply-To: <1588601168-27576-1-git-send-email-sai.pavan.boddu@xilinx.com>
Jumbo frames of size 10240 bytes is added.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
---
hw/net/cadence_gem.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index beb38ec..848be3f 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -313,6 +313,7 @@
#define DESC_1_RX_EOF 0x00008000
#define GEM_MODID_VALUE 0x00020118
+#define MAX_TX_FRAME_SIZE 10240
static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
{
@@ -1143,7 +1144,7 @@ static void gem_transmit(CadenceGEMState *s)
{
uint32_t desc[DESC_MAX_NUM_WORDS];
hwaddr packet_desc_addr;
- uint8_t tx_packet[2048];
+ uint8_t tx_packet[MAX_TX_FRAME_SIZE];
uint8_t *p;
unsigned total_bytes;
int q = 0;
@@ -1344,7 +1345,7 @@ static void gem_reset(DeviceState *d)
s->regs[GEM_RXPARTIALSF] = 0x000003ff;
s->regs[GEM_MODID] = s->revision;
s->regs[GEM_DESCONF] = 0x02500111;
- s->regs[GEM_DESCONF2] = 0x2ab13fff;
+ s->regs[GEM_DESCONF2] = 0x2ab12800;
s->regs[GEM_DESCONF5] = 0x002f2045;
s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
--
2.7.4
next prev parent reply other threads:[~2020-05-04 14:22 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-04 14:05 [PATCH v2 00/10] Cadence GEM Fixes Sai Pavan Boddu
2020-05-04 14:05 ` [PATCH v2 01/10] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-04 14:39 ` Edgar E. Iglesias
2020-05-06 9:55 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 02/10] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-04 14:43 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 03/10] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-04 14:32 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 04/10] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-04 14:57 ` Edgar E. Iglesias
2020-05-06 10:40 ` Sai Pavan Boddu
2020-05-04 14:06 ` [PATCH v2 05/10] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-04 15:02 ` Edgar E. Iglesias
2020-05-06 11:11 ` Sai Pavan Boddu
2020-05-04 14:06 ` Sai Pavan Boddu [this message]
2020-05-04 15:23 ` [PATCH v2 06/10] net: cadence_gem: Add support for jumbo frames Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 07/10] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-04 15:26 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 08/10] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-04 15:27 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 09/10] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-04 15:31 ` Edgar E. Iglesias
2020-05-04 14:06 ` [PATCH v2 10/10] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-04 15:33 ` Edgar E. Iglesias
2020-05-04 15:50 ` [PATCH v2 00/10] Cadence GEM Fixes Ramon Fried
2020-05-04 17:15 ` Sai Pavan Boddu
2020-05-05 8:31 ` no-reply
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