From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Tong Ho" <tong.ho@xilinx.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v4 00/12] Cadence GEM Fixes
Date: Tue, 12 May 2020 18:39:55 +0530 [thread overview]
Message-ID: <1589289007-23629-1-git-send-email-sai.pavan.boddu@xilinx.com> (raw)
Hi,
Following patch series fixes issues with priority queues,
Adds JUMBO Frame support,
Makes Debug statements compilable &
Fixes related to multicast frames.
Changes for V2:
Fixed build failure on fedora docker machine
Fix buggy debug print to use sized integer casting
Changes for V3:
1/10: Fixed debug statments to use %u and %zd
Remove rxoffset for buffer address
2/10: Add inline functions to get tx/rx queue base address.
4/10: fix read only mask
5/10: Move packet buffers to CadenceGEMState
6/10: Add JUMBO MAX LEN register
Changes for V4:
7/11: Fix up the existing code style in register defines
8/11: jumbo-max-len property sets the default value of jumbo frame
Add frame lenght checks for tx and rx
Sai Pavan Boddu (11):
net: cadence_gem: Fix debug statements
net: cadence_gem: Fix the queue address update during wrap around
net: cadence_gem: Fix irq update w.r.t queue
net: cadence_gem: Define access permission for interrupt registers
net: cadence_gem: Set ISR according to queue in use
net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState
net: cadence_gem: Fix up code style
net: cadence_gem: Add support for jumbo frames
net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg
net: cadence_gem: Update the reset value for interrupt mask register
net: cadence_gem: TX_LAST bit should be set by guest
Tong Ho (1):
net: cadence_gem: Fix RX address filtering
hw/net/cadence_gem.c | 453 ++++++++++++++++++++++++-------------------
include/hw/net/cadence_gem.h | 6 +
2 files changed, 260 insertions(+), 199 deletions(-)
--
2.7.4
next reply other threads:[~2020-05-12 13:20 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 13:09 Sai Pavan Boddu [this message]
2020-05-12 13:09 ` [PATCH v4 01/12] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 02/12] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 03/12] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 04/12] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 05/12] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 07/12] net: cadence_gem: Fix up code style Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 08/12] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 10/12] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 11/12] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 12/12] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
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