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From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Jason Wang" <jasowang@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Tong Ho" <tong.ho@xilinx.com>,
	"Ramon Fried" <rfried.dev@gmail.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v4 11/12] net: cadence_gem: TX_LAST bit should be set by guest
Date: Tue, 12 May 2020 18:40:06 +0530	[thread overview]
Message-ID: <1589289007-23629-12-git-send-email-sai.pavan.boddu@xilinx.com> (raw)
In-Reply-To: <1589289007-23629-1-git-send-email-sai.pavan.boddu@xilinx.com>

TX_LAST bit should not be set by hardware, its set by guest to inform
the last bd of the frame.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/net/cadence_gem.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 1b2e31d..00fe5d7 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -350,11 +350,6 @@ static inline unsigned tx_desc_get_last(uint32_t *desc)
     return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
 }
 
-static inline void tx_desc_set_last(uint32_t *desc)
-{
-    desc[1] |= DESC_1_TX_LAST;
-}
-
 static inline unsigned tx_desc_get_length(uint32_t *desc)
 {
     return desc[1] & DESC_1_LENGTH;
@@ -1293,7 +1288,6 @@ static void gem_transmit(CadenceGEMState *s)
 
             /* read next descriptor */
             if (tx_desc_get_wrap(desc)) {
-                tx_desc_set_last(desc);
 
                 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
                     packet_desc_addr = s->regs[GEM_TBQPH];
-- 
2.7.4



  parent reply	other threads:[~2020-05-12 13:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12 13:09 [PATCH v4 00/12] Cadence GEM Fixes Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 01/12] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 02/12] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 03/12] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 04/12] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 05/12] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 07/12] net: cadence_gem: Fix up code style Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 08/12] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 10/12] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-12 13:10 ` Sai Pavan Boddu [this message]
2020-05-12 13:10 ` [PATCH v4 12/12] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu

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