From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Alistair Francis" <Alistair.Francis@wdc.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Jason Wang" <jasowang@redhat.com>,
"Markus Armbruster" <armbru@redhat.com>,
"Philippe Mathieu-Daudé" <philmd@redhat.com>,
"Tong Ho" <tong.ho@xilinx.com>,
"Ramon Fried" <rfried.dev@gmail.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v4 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState
Date: Tue, 12 May 2020 18:40:01 +0530 [thread overview]
Message-ID: <1589289007-23629-7-git-send-email-sai.pavan.boddu@xilinx.com> (raw)
In-Reply-To: <1589289007-23629-1-git-send-email-sai.pavan.boddu@xilinx.com>
Moving this buffers to CadenceGEMState, as their size will be increased
more when JUMBO frames support is added.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
hw/net/cadence_gem.c | 38 +++++++++++++++++---------------------
include/hw/net/cadence_gem.h | 4 ++++
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index d3f7166..11e36d0 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -928,17 +928,14 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q)
*/
static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
- CadenceGEMState *s;
+ CadenceGEMState *s = qemu_get_nic_opaque(nc);
unsigned rxbufsize, bytes_to_copy;
unsigned rxbuf_offset;
- uint8_t rxbuf[2048];
uint8_t *rxbuf_ptr;
bool first_desc = true;
int maf;
int q = 0;
- s = qemu_get_nic_opaque(nc);
-
/* Is this destination MAC address "for us" ? */
maf = gem_mac_address_filter(s, buf);
if (maf == GEM_RX_REJECT) {
@@ -994,19 +991,19 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
} else {
unsigned crc_val;
- if (size > sizeof(rxbuf) - sizeof(crc_val)) {
- size = sizeof(rxbuf) - sizeof(crc_val);
+ if (size > MAX_FRAME_SIZE - sizeof(crc_val)) {
+ size = MAX_FRAME_SIZE - sizeof(crc_val);
}
bytes_to_copy = size;
/* The application wants the FCS field, which QEMU does not provide.
* We must try and calculate one.
*/
- memcpy(rxbuf, buf, size);
- memset(rxbuf + size, 0, sizeof(rxbuf) - size);
- rxbuf_ptr = rxbuf;
- crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
- memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
+ memcpy(s->rx_packet, buf, size);
+ memset(s->rx_packet + size, 0, MAX_FRAME_SIZE - size);
+ rxbuf_ptr = s->rx_packet;
+ crc_val = cpu_to_le32(crc32(0, s->rx_packet, MAX(size, 60)));
+ memcpy(s->rx_packet + size, &crc_val, sizeof(crc_val));
bytes_to_copy += 4;
size += 4;
@@ -1152,7 +1149,6 @@ static void gem_transmit(CadenceGEMState *s)
{
uint32_t desc[DESC_MAX_NUM_WORDS];
hwaddr packet_desc_addr;
- uint8_t tx_packet[2048];
uint8_t *p;
unsigned total_bytes;
int q = 0;
@@ -1168,7 +1164,7 @@ static void gem_transmit(CadenceGEMState *s)
* Packets scattered across multiple descriptors are gathered to this
* one contiguous buffer first.
*/
- p = tx_packet;
+ p = s->tx_packet;
total_bytes = 0;
for (q = s->num_priority_queues - 1; q >= 0; q--) {
@@ -1198,12 +1194,12 @@ static void gem_transmit(CadenceGEMState *s)
break;
}
- if (tx_desc_get_length(desc) > sizeof(tx_packet) -
- (p - tx_packet)) {
+ if (tx_desc_get_length(desc) > MAX_FRAME_SIZE -
+ (p - s->tx_packet)) {
DB_PRINT("TX descriptor @ 0x%" HWADDR_PRIx \
" too large: size 0x%x space 0x%zx\n",
packet_desc_addr, tx_desc_get_length(desc),
- sizeof(tx_packet) - (p - tx_packet));
+ MAX_FRAME_SIZE - (p - s->tx_packet));
break;
}
@@ -1248,24 +1244,24 @@ static void gem_transmit(CadenceGEMState *s)
/* Is checksum offload enabled? */
if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
- net_checksum_calculate(tx_packet, total_bytes);
+ net_checksum_calculate(s->tx_packet, total_bytes);
}
/* Update MAC statistics */
- gem_transmit_updatestats(s, tx_packet, total_bytes);
+ gem_transmit_updatestats(s, s->tx_packet, total_bytes);
/* Send the packet somewhere */
if (s->phy_loop || (s->regs[GEM_NWCTRL] &
GEM_NWCTRL_LOCALLOOP)) {
- gem_receive(qemu_get_queue(s->nic), tx_packet,
+ gem_receive(qemu_get_queue(s->nic), s->tx_packet,
total_bytes);
} else {
- qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
+ qemu_send_packet(qemu_get_queue(s->nic), s->tx_packet,
total_bytes);
}
/* Prepare for next packet */
- p = tx_packet;
+ p = s->tx_packet;
total_bytes = 0;
}
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 5c83036..eddac70 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -40,6 +40,8 @@
#define MAX_TYPE1_SCREENERS 16
#define MAX_TYPE2_SCREENERS 16
+#define MAX_FRAME_SIZE 2048
+
typedef struct CadenceGEMState {
/*< private >*/
SysBusDevice parent_obj;
@@ -80,6 +82,8 @@ typedef struct CadenceGEMState {
uint8_t can_rx_state; /* Debug only */
+ uint8_t tx_packet[MAX_FRAME_SIZE];
+ uint8_t rx_packet[MAX_FRAME_SIZE];
uint32_t rx_desc[MAX_PRIORITY_QUEUES][DESC_MAX_NUM_WORDS];
bool sar_active[4];
--
2.7.4
next prev parent reply other threads:[~2020-05-12 13:25 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-12 13:09 [PATCH v4 00/12] Cadence GEM Fixes Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 01/12] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 02/12] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 03/12] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-12 13:09 ` [PATCH v4 04/12] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 05/12] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-12 13:10 ` Sai Pavan Boddu [this message]
2020-05-12 13:10 ` [PATCH v4 07/12] net: cadence_gem: Fix up code style Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 08/12] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 10/12] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 11/12] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-12 13:10 ` [PATCH v4 12/12] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
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