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From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Alistair Francis" <Alistair.Francis@wdc.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Jason Wang" <jasowang@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Tong Ho" <tong.ho@xilinx.com>,
	"Ramon Fried" <rfried.dev@gmail.com>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Subject: [PATCH v5 00/12] Cadence GEM Fixes
Date: Tue, 12 May 2020 20:24:42 +0530	[thread overview]
Message-ID: <1589295294-26466-1-git-send-email-sai.pavan.boddu@xilinx.com> (raw)

Hi,

Following patch series fixes issues with priority queues,
Adds JUMBO Frame support,
Makes Debug statements compilable &
Fixes related to multicast frames.

Changes for V2:
	Fixed build failure on fedora docker machine
	Fix buggy debug print to use sized integer casting
Changes for V3:
	1/10: Fixed debug statments to use %u and %zd
	      Remove rxoffset for buffer address
	2/10: Add inline functions to get tx/rx queue base address.
	4/10: fix read only mask
	5/10: Move packet buffers to CadenceGEMState
	6/10: Add JUMBO MAX LEN register
Changes for V4:
	7/11: Fix up the existing code style in register defines
	8/11: jumbo-max-len property sets the default value of jumbo frame
	      Add frame lenght checks for tx and rx
Changes for V5:
	8/11: Add a cap on jumbo frame size and print guest errors if exceeded.
              Move jumo_max_len property into static properties section.

Sai Pavan Boddu (11):
  net: cadence_gem: Fix debug statements
  net: cadence_gem: Fix the queue address update during wrap around
  net: cadence_gem: Fix irq update w.r.t queue
  net: cadence_gem: Define access permission for interrupt registers
  net: cadence_gem: Set ISR according to queue in use
  net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState
  net: cadence_gem: Fix up code style
  net: cadence_gem: Add support for jumbo frames
  net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg
  net: cadence_gem: Update the reset value for interrupt mask register
  net: cadence_gem: TX_LAST bit should be set by guest

Tong Ho (1):
  net: cadence_gem: Fix RX address filtering

 hw/net/cadence_gem.c         | 458 ++++++++++++++++++++++++-------------------
 include/hw/net/cadence_gem.h |   6 +
 2 files changed, 265 insertions(+), 199 deletions(-)

-- 
2.7.4



             reply	other threads:[~2020-05-12 15:25 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-12 14:54 Sai Pavan Boddu [this message]
2020-05-12 14:54 ` [PATCH v5 01/12] net: cadence_gem: Fix debug statements Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 02/12] net: cadence_gem: Fix the queue address update during wrap around Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 03/12] net: cadence_gem: Fix irq update w.r.t queue Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 04/12] net: cadence_gem: Define access permission for interrupt registers Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 05/12] net: cadence_gem: Set ISR according to queue in use Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 06/12] net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 07/12] net: cadence_gem: Fix up code style Sai Pavan Boddu
2020-05-12 15:19   ` Edgar E. Iglesias
2020-05-12 14:54 ` [PATCH v5 08/12] net: cadence_gem: Add support for jumbo frames Sai Pavan Boddu
2020-05-12 15:19   ` Edgar E. Iglesias
2020-05-13  5:15     ` Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 09/12] net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 10/12] net: cadence_gem: Update the reset value for interrupt mask register Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 11/12] net: cadence_gem: TX_LAST bit should be set by guest Sai Pavan Boddu
2020-05-12 14:54 ` [PATCH v5 12/12] net: cadence_gem: Fix RX address filtering Sai Pavan Boddu
2020-05-14  6:47 ` [PATCH v5 00/12] Cadence GEM Fixes Jason Wang

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