* [PULL 0/6] MIPS queue for June 1st, 2020
@ 2020-06-01 12:18 Aleksandar Markovic
2020-06-01 12:18 ` [PULL 1/6] tests/Makefile: Fix description of "make check" Aleksandar Markovic
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Aleksandar Markovic @ 2020-06-01 12:18 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel
The following changes since commit 4ec2a1f53e8aaa22924614b64dde97321126943e:
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-05-30' into staging (2020-05-31 20:43:45 +0100)
are available in the git repository at:
https://github.com/AMarkovic/qemu
for you to fetch changes up to a08d60bc6c2b6469368fff3d38dd5ddd16dd36be:
hw/mips: fuloong2e: Set preferred page size to 16KB (2020-06-01 13:28:21 +0200)
----------------------------------------------------------------
MIPS queue for June 1st, 2020
Highlights:
- setting Fuloong 2E preffered page size to a different value
- preparation for adding KVM support for Longsoon 3
- other minor changes
- a checkpatch warning is known and should be ignored
----------------------------------------------------------------
Huacai Chen (6):
tests/Makefile: Fix description of "make check"
configure: Add KVM target support for MIPS64
hw/mips: Add CPU IRQ3 delivery for KVM
target/mips: Add more CP0 register for save/restore
target/mips: Support variable page size
hw/mips: fuloong2e: Set preferred page size to 16KB
configure | 2 +-
target/mips/cpu-param.h | 5 ++
hw/mips/fuloong2e.c | 1 +
hw/mips/mips_int.c | 2 +-
target/mips/kvm.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++++
target/mips/machine.c | 6 +-
tests/Makefile.include | 2 +-
7 files changed, 225 insertions(+), 5 deletions(-)
--
2.7.4
^ permalink raw reply [flat|nested] 14+ messages in thread* [PULL 1/6] tests/Makefile: Fix description of "make check" 2020-06-01 12:18 [PULL 0/6] MIPS queue for June 1st, 2020 Aleksandar Markovic @ 2020-06-01 12:18 ` Aleksandar Markovic 2020-06-01 12:18 ` [PULL 2/6] configure: Add KVM target support for MIPS64 Aleksandar Markovic ` (5 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:18 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel From: Huacai Chen <zltjiangshi@gmail.com> The description of "make check" is out-of-date, so fix it by adding block and softfloat. Reviewed-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1588674291-6486-1-git-send-email-chenhc@lemote.com> --- tests/Makefile.include | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/Makefile.include b/tests/Makefile.include index a00ccc9..6e3d637 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -4,7 +4,7 @@ check-help: @echo "Regression testing targets:" @echo - @echo " $(MAKE) check Run unit, qapi-schema, qtest and decodetree" + @echo " $(MAKE) check Run block, qapi-schema, unit, softfloat, qtest and decodetree tests" @echo @echo " $(MAKE) check-qtest-TARGET Run qtest tests for given target" @echo " $(MAKE) check-qtest Run qtest tests" -- 2.7.4 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PULL 2/6] configure: Add KVM target support for MIPS64 2020-06-01 12:18 [PULL 0/6] MIPS queue for June 1st, 2020 Aleksandar Markovic 2020-06-01 12:18 ` [PULL 1/6] tests/Makefile: Fix description of "make check" Aleksandar Markovic @ 2020-06-01 12:18 ` Aleksandar Markovic 2020-06-01 12:18 ` [PULL 3/6] hw/mips: Add CPU IRQ3 delivery for KVM Aleksandar Markovic ` (4 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:18 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel From: Huacai Chen <zltjiangshi@gmail.com> Preparing for Loongson-3 virtualization, add KVM target support for MIPS64 in configure script. Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1588501221-1205-2-git-send-email-chenhc@lemote.com> --- configure | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index af2ba83..f087d2b 100755 --- a/configure +++ b/configure @@ -198,7 +198,7 @@ supported_kvm_target() { arm:arm | aarch64:aarch64 | \ i386:i386 | i386:x86_64 | i386:x32 | \ x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \ - mips:mips | mipsel:mips | \ + mips:mips | mipsel:mips | mips64:mips | mips64el:mips | \ ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \ s390x:s390x) return 0 -- 2.7.4 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PULL 3/6] hw/mips: Add CPU IRQ3 delivery for KVM 2020-06-01 12:18 [PULL 0/6] MIPS queue for June 1st, 2020 Aleksandar Markovic 2020-06-01 12:18 ` [PULL 1/6] tests/Makefile: Fix description of "make check" Aleksandar Markovic 2020-06-01 12:18 ` [PULL 2/6] configure: Add KVM target support for MIPS64 Aleksandar Markovic @ 2020-06-01 12:18 ` Aleksandar Markovic 2020-06-01 12:18 ` [PULL 4/6] target/mips: Add more CP0 register for save/restore Aleksandar Markovic ` (3 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:18 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel From: Huacai Chen <zltjiangshi@gmail.com> Currently, KVM/MIPS only deliver I/O interrupt via IP2, this patch add IP3 delivery as well, because Loongson-3 based machine use both IRQ2 (CPU's IP2) and IRQ3 (CPU's IP3). Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1588501221-1205-4-git-send-email-chenhc@lemote.com> --- hw/mips/mips_int.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 4a1bf84..0f9c6f0 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -51,7 +51,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); } - if (kvm_enabled() && irq == 2) { + if (kvm_enabled() && (irq == 2 || irq == 3)) { kvm_mips_set_interrupt(cpu, irq, level); } -- 2.7.4 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PULL 4/6] target/mips: Add more CP0 register for save/restore 2020-06-01 12:18 [PULL 0/6] MIPS queue for June 1st, 2020 Aleksandar Markovic ` (2 preceding siblings ...) 2020-06-01 12:18 ` [PULL 3/6] hw/mips: Add CPU IRQ3 delivery for KVM Aleksandar Markovic @ 2020-06-01 12:18 ` Aleksandar Markovic 2020-06-01 12:18 ` [PULL 5/6] target/mips: Support variable page size Aleksandar Markovic ` (2 subsequent siblings) 6 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:18 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel From: Huacai Chen <zltjiangshi@gmail.com> Add more CP0 register for save/restore, including: EBase, XContext, PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1588501221-1205-6-git-send-email-chenhc@lemote.com> --- target/mips/kvm.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++++++ target/mips/machine.c | 6 +- 2 files changed, 216 insertions(+), 2 deletions(-) diff --git a/target/mips/kvm.c b/target/mips/kvm.c index de3e26e..96cfa10 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) +#define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) @@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) +#define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) +#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) +#define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) +#define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) +#define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) +#define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) +#define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, int32_t *addr) @@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, (1U << CP0C5_UFE) | \ (1U << CP0C5_FRE) | \ (1U << CP0C5_UFR)) +#define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ + (0x3fU << CP0C6_KPOS) | \ + (1U << CP0C6_KE) | \ + (1U << CP0C6_VTLBONLY) | \ + (1U << CP0C6_LASX) | \ + (1U << CP0C6_SSEN) | \ + (1U << CP0C6_DISDRTIME) | \ + (1U << CP0C6_PIXNUEN) | \ + (1U << CP0C6_SCRAND) | \ + (1U << CP0C6_LLEXCEN) | \ + (1U << CP0C6_DISVC) | \ + (1U << CP0C6_VCLRU) | \ + (1U << CP0C6_DCLRU) | \ + (1U << CP0C6_PIXUEN) | \ + (1U << CP0C6_DISBLKLYEN) | \ + (1U << CP0C6_UMEMUALEN) | \ + (1U << CP0C6_SFBEN) | \ + (1U << CP0C6_FLTINT) | \ + (1U << CP0C6_VLTINT) | \ + (1U << CP0C6_DISBTB) | \ + (3U << CP0C6_STPREFCTL) | \ + (1U << CP0C6_INSTPREF) | \ + (1U << CP0C6_DATAPREF)) static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, int32_t *addr, int32_t mask) @@ -729,6 +767,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_RANDOM (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, &env->CP0_Context); if (err < 0) { @@ -747,11 +790,40 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, + &env->CP0_PageGrain); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PAGEGRAIN (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, + &env->CP0_PWBase); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PWBASE (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, + &env->CP0_PWField); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PWField (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, + &env->CP0_PWSize); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PWSIZE (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); if (err < 0) { DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PWCTL (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); if (err < 0) { DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); @@ -799,6 +871,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_EBASE (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0, KVM_REG_MIPS_CP0_CONFIG_MASK); @@ -841,12 +918,61 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); ret = err; } + err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, + &env->CP0_Config6, + KVM_REG_MIPS_CP0_CONFIG6_MASK); + if (err < 0) { + DPRINTF("%s: Failed to change CP0_CONFIG6 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, + &env->CP0_XContext); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_XCONTEXT (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, &env->CP0_ErrorEPC); if (err < 0) { DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, + &env->CP0_KScratch[0]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH1 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, + &env->CP0_KScratch[1]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH2 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, + &env->CP0_KScratch[2]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH3 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, + &env->CP0_KScratch[3]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH4 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, + &env->CP0_KScratch[4]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH5 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, + &env->CP0_KScratch[5]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH6 (%d)\n", __func__, err); + ret = err; + } return ret; } @@ -862,6 +988,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_RANDOM (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, &env->CP0_Context); if (err < 0) { @@ -880,11 +1011,40 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, + &env->CP0_PageGrain); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PAGEGRAIN (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, + &env->CP0_PWBase); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PWBASE (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, + &env->CP0_PWField); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PWFIELD (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, + &env->CP0_PWSize); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PWSIZE (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); if (err < 0) { DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PWCtl (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); if (err < 0) { DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); @@ -932,6 +1092,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_EBASE (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); if (err < 0) { DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); @@ -962,12 +1127,59 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, &env->CP0_Config6); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_CONFIG6 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, + &env->CP0_XContext); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_XCONTEXT (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, &env->CP0_ErrorEPC); if (err < 0) { DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, + &env->CP0_KScratch[0]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH1 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, + &env->CP0_KScratch[1]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH2 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, + &env->CP0_KScratch[2]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH3 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, + &env->CP0_KScratch[3]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH4 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, + &env->CP0_KScratch[4]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH5 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, + &env->CP0_KScratch[5]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH6 (%d)\n", __func__, err); + ret = err; + } return ret; } diff --git a/target/mips/machine.c b/target/mips/machine.c index 8d5b18b..5b23e3e 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = { const VMStateDescription vmstate_mips_cpu = { .name = "cpu", - .version_id = 19, - .minimum_version_id = 19, + .version_id = 20, + .minimum_version_id = 20, .post_load = cpu_post_load, .fields = (VMStateField[]) { /* Active TC */ @@ -289,6 +289,8 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_INT32(env.CP0_Config1, MIPSCPU), VMSTATE_INT32(env.CP0_Config2, MIPSCPU), VMSTATE_INT32(env.CP0_Config3, MIPSCPU), + VMSTATE_INT32(env.CP0_Config4, MIPSCPU), + VMSTATE_INT32(env.CP0_Config5, MIPSCPU), VMSTATE_INT32(env.CP0_Config6, MIPSCPU), VMSTATE_INT32(env.CP0_Config7, MIPSCPU), VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU), -- 2.7.4 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PULL 5/6] target/mips: Support variable page size 2020-06-01 12:18 [PULL 0/6] MIPS queue for June 1st, 2020 Aleksandar Markovic ` (3 preceding siblings ...) 2020-06-01 12:18 ` [PULL 4/6] target/mips: Add more CP0 register for save/restore Aleksandar Markovic @ 2020-06-01 12:18 ` Aleksandar Markovic 2020-06-01 12:18 ` [PULL 6/6] hw/mips: fuloong2e: Set preferred page size to 16KB Aleksandar Markovic 2020-06-01 12:20 ` [PULL 0/6] MIPS queue for June 1st, 2020 Peter Maydell 6 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:18 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel From: Huacai Chen <chenhc@lemote.com> Traditionally, MIPS use 4KB page size, but Loongson prefer 16KB page size in system emulator. So, let's define TARGET_PAGE_BITS_VARY and TARGET_PAGE_BITS_MIN to support variable page size. Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1586337380-25217-1-git-send-email-chenhc@lemote.com> --- target/mips/cpu-param.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h index 308660d..9c4a6ea 100644 --- a/target/mips/cpu-param.h +++ b/target/mips/cpu-param.h @@ -23,7 +23,12 @@ # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif #endif +#ifdef CONFIG_USER_ONLY #define TARGET_PAGE_BITS 12 +#else +#define TARGET_PAGE_BITS_VARY +#define TARGET_PAGE_BITS_MIN 12 +#endif #define NB_MMU_MODES 4 #endif -- 2.7.4 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PULL 6/6] hw/mips: fuloong2e: Set preferred page size to 16KB 2020-06-01 12:18 [PULL 0/6] MIPS queue for June 1st, 2020 Aleksandar Markovic ` (4 preceding siblings ...) 2020-06-01 12:18 ` [PULL 5/6] target/mips: Support variable page size Aleksandar Markovic @ 2020-06-01 12:18 ` Aleksandar Markovic 2020-06-01 12:20 ` [PULL 0/6] MIPS queue for June 1st, 2020 Peter Maydell 6 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:18 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel From: Huacai Chen <chenhc@lemote.com> Loongson processor prefers 16KB page size in system emulator, so let's define mc->minimum_page_bits to 14. Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhc@lemote.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1586337380-25217-2-git-send-email-chenhc@lemote.com> --- hw/mips/fuloong2e.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index f583c44..7a65166 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -392,6 +392,7 @@ static void mips_fuloong2e_machine_init(MachineClass *mc) mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E"); mc->default_ram_size = 256 * MiB; mc->default_ram_id = "fuloong2e.ram"; + mc->minimum_page_bits = 14; } DEFINE_MACHINE("fuloong2e", mips_fuloong2e_machine_init) -- 2.7.4 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PULL 0/6] MIPS queue for June 1st, 2020 2020-06-01 12:18 [PULL 0/6] MIPS queue for June 1st, 2020 Aleksandar Markovic ` (5 preceding siblings ...) 2020-06-01 12:18 ` [PULL 6/6] hw/mips: fuloong2e: Set preferred page size to 16KB Aleksandar Markovic @ 2020-06-01 12:20 ` Peter Maydell 2020-06-01 12:45 ` Aleksandar Markovic 6 siblings, 1 reply; 14+ messages in thread From: Peter Maydell @ 2020-06-01 12:20 UTC (permalink / raw) To: Aleksandar Markovic; +Cc: QEMU Developers On Mon, 1 Jun 2020 at 13:18, Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> wrote: > > The following changes since commit 4ec2a1f53e8aaa22924614b64dde97321126943e: > > Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-05-30' into staging (2020-05-31 20:43:45 +0100) > > are available in the git repository at: > > https://github.com/AMarkovic/qemu > > for you to fetch changes up to a08d60bc6c2b6469368fff3d38dd5ddd16dd36be: > > hw/mips: fuloong2e: Set preferred page size to 16KB (2020-06-01 13:28:21 +0200) Hi; something seems to have gone wrong with your pullreq: it is missing the tag name after the git repository URL... thanks -- PMM ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PULL 0/6] MIPS queue for June 1st, 2020 2020-06-01 12:20 ` [PULL 0/6] MIPS queue for June 1st, 2020 Peter Maydell @ 2020-06-01 12:45 ` Aleksandar Markovic 0 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:45 UTC (permalink / raw) To: Peter Maydell; +Cc: Aleksandar Markovic, QEMU Developers On Mon, Jun 1, 2020 at 2:21 PM Peter Maydell <peter.maydell@linaro.org> wrote: > > On Mon, 1 Jun 2020 at 13:18, Aleksandar Markovic > <aleksandar.qemu.devel@gmail.com> wrote: > > > > The following changes since commit 4ec2a1f53e8aaa22924614b64dde97321126943e: > > > > Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-05-30' into staging (2020-05-31 20:43:45 +0100) > > > > are available in the git repository at: > > > > https://github.com/AMarkovic/qemu > > > > for you to fetch changes up to a08d60bc6c2b6469368fff3d38dd5ddd16dd36be: > > > > hw/mips: fuloong2e: Set preferred page size to 16KB (2020-06-01 13:28:21 +0200) > > Hi; something seems to have gone wrong with your pullreq: it is > missing the tag name after the git repository URL... > True. Wrong "git request-pull" command. My bad, truly sorry. Just sent v2, since there was no problem with patches by themselves. Hopefully it will work. I have recently problems of various kinds related to remote work, and changing email address(es) (again). I really hope this v2 will be good for you. Thanks, Aleksandar > thanks > -- PMM > ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PULL 0/6] MIPS queue for June 1st, 2020 @ 2020-06-01 12:43 Aleksandar Markovic 2020-06-01 12:43 ` [PULL 4/6] target/mips: Add more CP0 register for save/restore Aleksandar Markovic 0 siblings, 1 reply; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:43 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel The following changes since commit 4ec2a1f53e8aaa22924614b64dde97321126943e: Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2020-05-30' into staging (2020-05-31 20:43:45 +0100) are available in the git repository at: https://github.com/AMarkovic/qemu tags/mips-queue-june-01-2020 for you to fetch changes up to a08d60bc6c2b6469368fff3d38dd5ddd16dd36be: hw/mips: fuloong2e: Set preferred page size to 16KB (2020-06-01 13:28:21 +0200) ---------------------------------------------------------------- MIPS queue for June 1st, 2020 Highlights: - setting Fuloong 2E preffered page size to a different value - preparation for adding KVM support for Longsoon 3 - other minor changes - a checkpatch warning is known and should be ignored ---------------------------------------------------------------- Huacai Chen (6): tests/Makefile: Fix description of "make check" configure: Add KVM target support for MIPS64 hw/mips: Add CPU IRQ3 delivery for KVM target/mips: Add more CP0 register for save/restore target/mips: Support variable page size hw/mips: fuloong2e: Set preferred page size to 16KB configure | 2 +- target/mips/cpu-param.h | 5 ++ hw/mips/fuloong2e.c | 1 + hw/mips/mips_int.c | 2 +- target/mips/kvm.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++++ target/mips/machine.c | 6 +- tests/Makefile.include | 2 +- 7 files changed, 225 insertions(+), 5 deletions(-) -- 2.7.4 ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PULL 4/6] target/mips: Add more CP0 register for save/restore 2020-06-01 12:43 Aleksandar Markovic @ 2020-06-01 12:43 ` Aleksandar Markovic 2020-06-11 9:50 ` Alex Bennée 0 siblings, 1 reply; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-01 12:43 UTC (permalink / raw) To: qemu-devel; +Cc: peter.maydell, aleksandar.qemu.devel From: Huacai Chen <zltjiangshi@gmail.com> Add more CP0 register for save/restore, including: EBase, XContext, PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> Message-Id: <1588501221-1205-6-git-send-email-chenhc@lemote.com> --- target/mips/kvm.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++++++ target/mips/machine.c | 6 +- 2 files changed, 216 insertions(+), 2 deletions(-) diff --git a/target/mips/kvm.c b/target/mips/kvm.c index de3e26e..96cfa10 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) +#define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) @@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) +#define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) +#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) +#define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) +#define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) +#define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) +#define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) +#define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, int32_t *addr) @@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, (1U << CP0C5_UFE) | \ (1U << CP0C5_FRE) | \ (1U << CP0C5_UFR)) +#define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ + (0x3fU << CP0C6_KPOS) | \ + (1U << CP0C6_KE) | \ + (1U << CP0C6_VTLBONLY) | \ + (1U << CP0C6_LASX) | \ + (1U << CP0C6_SSEN) | \ + (1U << CP0C6_DISDRTIME) | \ + (1U << CP0C6_PIXNUEN) | \ + (1U << CP0C6_SCRAND) | \ + (1U << CP0C6_LLEXCEN) | \ + (1U << CP0C6_DISVC) | \ + (1U << CP0C6_VCLRU) | \ + (1U << CP0C6_DCLRU) | \ + (1U << CP0C6_PIXUEN) | \ + (1U << CP0C6_DISBLKLYEN) | \ + (1U << CP0C6_UMEMUALEN) | \ + (1U << CP0C6_SFBEN) | \ + (1U << CP0C6_FLTINT) | \ + (1U << CP0C6_VLTINT) | \ + (1U << CP0C6_DISBTB) | \ + (3U << CP0C6_STPREFCTL) | \ + (1U << CP0C6_INSTPREF) | \ + (1U << CP0C6_DATAPREF)) static inline int kvm_mips_change_one_reg(CPUState *cs, uint64_t reg_id, int32_t *addr, int32_t mask) @@ -729,6 +767,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to put CP0_INDEX (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_RANDOM (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, &env->CP0_Context); if (err < 0) { @@ -747,11 +790,40 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to put CP0_PAGEMASK (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, + &env->CP0_PageGrain); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PAGEGRAIN (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, + &env->CP0_PWBase); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PWBASE (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, + &env->CP0_PWField); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PWField (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, + &env->CP0_PWSize); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PWSIZE (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); if (err < 0) { DPRINTF("%s: Failed to put CP0_WIRED (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_PWCTL (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); if (err < 0) { DPRINTF("%s: Failed to put CP0_HWRENA (%d)\n", __func__, err); @@ -799,6 +871,11 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to put CP0_PRID (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_EBASE (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0, KVM_REG_MIPS_CP0_CONFIG_MASK); @@ -841,12 +918,61 @@ static int kvm_mips_put_cp0_registers(CPUState *cs, int level) DPRINTF("%s: Failed to change CP0_CONFIG5 (%d)\n", __func__, err); ret = err; } + err = kvm_mips_change_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, + &env->CP0_Config6, + KVM_REG_MIPS_CP0_CONFIG6_MASK); + if (err < 0) { + DPRINTF("%s: Failed to change CP0_CONFIG6 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, + &env->CP0_XContext); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_XCONTEXT (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, &env->CP0_ErrorEPC); if (err < 0) { DPRINTF("%s: Failed to put CP0_ERROREPC (%d)\n", __func__, err); ret = err; } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, + &env->CP0_KScratch[0]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH1 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, + &env->CP0_KScratch[1]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH2 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, + &env->CP0_KScratch[2]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH3 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, + &env->CP0_KScratch[3]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH4 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, + &env->CP0_KScratch[4]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH5 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_put_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, + &env->CP0_KScratch[5]); + if (err < 0) { + DPRINTF("%s: Failed to put CP0_KSCRATCH6 (%d)\n", __func__, err); + ret = err; + } return ret; } @@ -862,6 +988,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_INDEX (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_RANDOM, &env->CP0_Random); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_RANDOM (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_CONTEXT, &env->CP0_Context); if (err < 0) { @@ -880,11 +1011,40 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_PAGEMASK (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PAGEGRAIN, + &env->CP0_PageGrain); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PAGEGRAIN (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWBASE, + &env->CP0_PWBase); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PWBASE (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWFIELD, + &env->CP0_PWField); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PWFIELD (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_PWSIZE, + &env->CP0_PWSize); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PWSIZE (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_WIRED, &env->CP0_Wired); if (err < 0) { DPRINTF("%s: Failed to get CP0_WIRED (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_PWCTL, &env->CP0_PWCtl); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_PWCtl (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_HWRENA, &env->CP0_HWREna); if (err < 0) { DPRINTF("%s: Failed to get CP0_HWRENA (%d)\n", __func__, err); @@ -932,6 +1092,11 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_PRID (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_EBASE, &env->CP0_EBase); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_EBASE (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG, &env->CP0_Config0); if (err < 0) { DPRINTF("%s: Failed to get CP0_CONFIG (%d)\n", __func__, err); @@ -962,12 +1127,59 @@ static int kvm_mips_get_cp0_registers(CPUState *cs) DPRINTF("%s: Failed to get CP0_CONFIG5 (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_reg(cs, KVM_REG_MIPS_CP0_CONFIG6, &env->CP0_Config6); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_CONFIG6 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_XCONTEXT, + &env->CP0_XContext); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_XCONTEXT (%d)\n", __func__, err); + ret = err; + } err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_ERROREPC, &env->CP0_ErrorEPC); if (err < 0) { DPRINTF("%s: Failed to get CP0_ERROREPC (%d)\n", __func__, err); ret = err; } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH1, + &env->CP0_KScratch[0]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH1 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH2, + &env->CP0_KScratch[1]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH2 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH3, + &env->CP0_KScratch[2]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH3 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH4, + &env->CP0_KScratch[3]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH4 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH5, + &env->CP0_KScratch[4]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH5 (%d)\n", __func__, err); + ret = err; + } + err = kvm_mips_get_one_ulreg(cs, KVM_REG_MIPS_CP0_KSCRATCH6, + &env->CP0_KScratch[5]); + if (err < 0) { + DPRINTF("%s: Failed to get CP0_KSCRATCH6 (%d)\n", __func__, err); + ret = err; + } return ret; } diff --git a/target/mips/machine.c b/target/mips/machine.c index 8d5b18b..5b23e3e 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -212,8 +212,8 @@ const VMStateDescription vmstate_tlb = { const VMStateDescription vmstate_mips_cpu = { .name = "cpu", - .version_id = 19, - .minimum_version_id = 19, + .version_id = 20, + .minimum_version_id = 20, .post_load = cpu_post_load, .fields = (VMStateField[]) { /* Active TC */ @@ -289,6 +289,8 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_INT32(env.CP0_Config1, MIPSCPU), VMSTATE_INT32(env.CP0_Config2, MIPSCPU), VMSTATE_INT32(env.CP0_Config3, MIPSCPU), + VMSTATE_INT32(env.CP0_Config4, MIPSCPU), + VMSTATE_INT32(env.CP0_Config5, MIPSCPU), VMSTATE_INT32(env.CP0_Config6, MIPSCPU), VMSTATE_INT32(env.CP0_Config7, MIPSCPU), VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU), -- 2.7.4 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PULL 4/6] target/mips: Add more CP0 register for save/restore 2020-06-01 12:43 ` [PULL 4/6] target/mips: Add more CP0 register for save/restore Aleksandar Markovic @ 2020-06-11 9:50 ` Alex Bennée 2020-06-11 10:00 ` Aleksandar Markovic ` (2 more replies) 0 siblings, 3 replies; 14+ messages in thread From: Alex Bennée @ 2020-06-11 9:50 UTC (permalink / raw) To: Aleksandar Markovic; +Cc: peter.maydell, qemu-devel Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> writes: > From: Huacai Chen <zltjiangshi@gmail.com> > > Add more CP0 register for save/restore, including: EBase, XContext, > PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > Message-Id: <1588501221-1205-6-git-send-email-chenhc@lemote.com> It seems while our mips cross build has been broken this commit has caused a build regression: make docker-test-build@debian-mips-cross J=30 Results in: /tmp/qemu-test/src/target/mips/kvm.c: In function 'kvm_mips_put_cp0_registers': /tmp/qemu-test/src/target/mips/kvm.c:412:49: error: 'CP0C6_BPPASS' undeclared (first use in this function); did you mean 'CP0C3_LPA'? #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ ^~~~~~~~~~~~ /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' KVM_REG_MIPS_CP0_CONFIG6_MASK); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /tmp/qemu-test/src/target/mips/kvm.c:412:49: note: each undeclared identifier is reported only once for each function it appears in #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ ^~~~~~~~~~~~ /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' KVM_REG_MIPS_CP0_CONFIG6_MASK); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /tmp/qemu-test/src/target/mips/kvm.c:413:52: error: 'CP0C6_KPOS' undeclared (first use in this function); did you mean 'CP0C3_IPLV'? (0x3fU << CP0C6_KPOS) | \ ^~~~~~~~~~ /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' KVM_REG_MIPS_CP0_CONFIG6_MASK); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ /tmp/qemu-test/src/target/mips/kvm.c:414:49: error: 'CP0C6_KE' undeclared (first use in this function); did you mean 'CP0C4_AE'? (1U << CP0C6_KE) | \ ^~~~~~~~ /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' KVM_REG_MIPS_CP0_CONFIG6_MASK); > --- > target/mips/kvm.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++++++ > target/mips/machine.c | 6 +- > 2 files changed, 216 insertions(+), 2 deletions(-) > > diff --git a/target/mips/kvm.c b/target/mips/kvm.c > index de3e26e..96cfa10 100644 > --- a/target/mips/kvm.c > +++ b/target/mips/kvm.c > @@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) > (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) > > #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) > +#define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) > #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) > #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) > #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) > +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) > +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) > +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) > +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) > #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) > +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) > #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) > #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) > #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) > @@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) > #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) > #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) > #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) > +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) > #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) > #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) > #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) > #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) > #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) > #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) > +#define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) > +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) > #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) > +#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) > +#define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) > +#define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) > +#define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) > +#define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) > +#define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) > > static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, > int32_t *addr) > @@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, > (1U << CP0C5_UFE) | \ > (1U << CP0C5_FRE) | \ > (1U << CP0C5_UFR)) > +#define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > + (0x3fU << CP0C6_KPOS) | \ > + (1U << CP0C6_KE) | \ > + (1U << CP0C6_VTLBONLY) | \ > + (1U << CP0C6_LASX) | \ > + (1U << CP0C6_SSEN) | \ > + (1U << CP0C6_DISDRTIME) | \ > + (1U << CP0C6_PIXNUEN) | \ > + (1U << CP0C6_SCRAND) | \ > + (1U << CP0C6_LLEXCEN) | \ > + (1U << CP0C6_DISVC) | \ > + (1U << CP0C6_VCLRU) | \ > + (1U << CP0C6_DCLRU) | \ > + (1U << CP0C6_PIXUEN) | \ > + (1U << CP0C6_DISBLKLYEN) | \ > + (1U << CP0C6_UMEMUALEN) | \ > + (1U << CP0C6_SFBEN) | \ > + (1U << CP0C6_FLTINT) | \ > + (1U << CP0C6_VLTINT) | \ > + (1U << CP0C6_DISBTB) | \ > + (3U << CP0C6_STPREFCTL) | \ > + (1U << CP0C6_INSTPREF) | \ > + (1U << CP0C6_DATAPREF)) It seems a lot of the defines here aren't in this commit. Was one missed? -- Alex Bennée ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PULL 4/6] target/mips: Add more CP0 register for save/restore 2020-06-11 9:50 ` Alex Bennée @ 2020-06-11 10:00 ` Aleksandar Markovic 2020-06-11 10:58 ` Aleksandar Markovic 2020-06-11 18:36 ` Aleksandar Markovic 2 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-11 10:00 UTC (permalink / raw) To: Alex Bennée; +Cc: Peter Maydell, QEMU Developers чет, 11. јун 2020. у 11:50 Alex Bennée <alex.bennee@linaro.org> је написао/ла: > > > Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> writes: > > > From: Huacai Chen <zltjiangshi@gmail.com> > > > > Add more CP0 register for save/restore, including: EBase, XContext, > > PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > > Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > > Message-Id: <1588501221-1205-6-git-send-email-chenhc@lemote.com> > > It seems while our mips cross build has been broken this commit has > caused a build regression: > I'll take a look, but would ask Huacai to do the same. Thanks, Aleksandar > make docker-test-build@debian-mips-cross J=30 > > Results in: > > /tmp/qemu-test/src/target/mips/kvm.c: In function 'kvm_mips_put_cp0_registers': > /tmp/qemu-test/src/target/mips/kvm.c:412:49: error: 'CP0C6_BPPASS' undeclared (first use in this function); did you mean 'CP0C3_LPA'? > #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > ^~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:412:49: note: each undeclared identifier is reported only once for each function it appears in > #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > ^~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:413:52: error: 'CP0C6_KPOS' undeclared (first use in this function); did you mean 'CP0C3_IPLV'? > (0x3fU << CP0C6_KPOS) | \ > ^~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:414:49: error: 'CP0C6_KE' undeclared (first use in this function); did you mean 'CP0C4_AE'? > (1U << CP0C6_KE) | \ > ^~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > > > > --- > > target/mips/kvm.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++++++ > > target/mips/machine.c | 6 +- > > 2 files changed, 216 insertions(+), 2 deletions(-) > > > > diff --git a/target/mips/kvm.c b/target/mips/kvm.c > > index de3e26e..96cfa10 100644 > > --- a/target/mips/kvm.c > > +++ b/target/mips/kvm.c > > @@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) > > (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) > > > > #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) > > +#define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) > > #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) > > #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) > > #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) > > +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) > > +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) > > +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) > > +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) > > #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) > > +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) > > #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) > > #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) > > #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) > > @@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) > > #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) > > #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) > > #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) > > +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) > > #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) > > #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) > > #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) > > #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) > > #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) > > #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) > > +#define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) > > +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) > > #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) > > +#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) > > +#define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) > > +#define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) > > +#define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) > > +#define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) > > +#define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) > > > > static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, > > int32_t *addr) > > @@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, > > (1U << CP0C5_UFE) | \ > > (1U << CP0C5_FRE) | \ > > (1U << CP0C5_UFR)) > > +#define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > > + (0x3fU << CP0C6_KPOS) | \ > > + (1U << CP0C6_KE) | \ > > + (1U << CP0C6_VTLBONLY) | \ > > + (1U << CP0C6_LASX) | \ > > + (1U << CP0C6_SSEN) | \ > > + (1U << CP0C6_DISDRTIME) | \ > > + (1U << CP0C6_PIXNUEN) | \ > > + (1U << CP0C6_SCRAND) | \ > > + (1U << CP0C6_LLEXCEN) | \ > > + (1U << CP0C6_DISVC) | \ > > + (1U << CP0C6_VCLRU) | \ > > + (1U << CP0C6_DCLRU) | \ > > + (1U << CP0C6_PIXUEN) | \ > > + (1U << CP0C6_DISBLKLYEN) | \ > > + (1U << CP0C6_UMEMUALEN) | \ > > + (1U << CP0C6_SFBEN) | \ > > + (1U << CP0C6_FLTINT) | \ > > + (1U << CP0C6_VLTINT) | \ > > + (1U << CP0C6_DISBTB) | \ > > + (3U << CP0C6_STPREFCTL) | \ > > + (1U << CP0C6_INSTPREF) | \ > > + (1U << CP0C6_DATAPREF)) > > It seems a lot of the defines here aren't in this commit. Was one missed? > > -- > Alex Bennée ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PULL 4/6] target/mips: Add more CP0 register for save/restore 2020-06-11 9:50 ` Alex Bennée 2020-06-11 10:00 ` Aleksandar Markovic @ 2020-06-11 10:58 ` Aleksandar Markovic 2020-06-11 18:36 ` Aleksandar Markovic 2 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-11 10:58 UTC (permalink / raw) To: Alex Bennée; +Cc: Peter Maydell, QEMU Developers [-- Attachment #1: Type: text/plain, Size: 8433 bytes --] чет, 11. јун 2020. у 11:50 Alex Bennée <alex.bennee@linaro.org> је написао/ла: > > > Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> writes: > > > From: Huacai Chen <zltjiangshi@gmail.com> > > > > Add more CP0 register for save/restore, including: EBase, XContext, > > PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > > Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > > Message-Id: <1588501221-1205-6-git-send-email-chenhc@lemote.com> > > It seems while our mips cross build has been broken this commit has > caused a build regression: > It appears that the fix for this issue is already a part of my pull request from Tuesday evening: https://github.com/AMarkovic/qemu/commit/af868995e1b7641577300d1342ede452ef0c5565 There should be need for any additional patch to fix the issue. Of course, this wouldn't have happened, if I had been more careful. My bad. Hopefully everything will work without any problems and glitches after the pull request is applied. Thanks, Aleksandar > make docker-test-build@debian-mips-cross J=30 > > Results in: > > /tmp/qemu-test/src/target/mips/kvm.c: In function 'kvm_mips_put_cp0_registers': > /tmp/qemu-test/src/target/mips/kvm.c:412:49: error: 'CP0C6_BPPASS' undeclared (first use in this function); did you mean 'CP0C3_LPA'? > #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > ^~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:412:49: note: each undeclared identifier is reported only once for each function it appears in > #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > ^~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:413:52: error: 'CP0C6_KPOS' undeclared (first use in this function); did you mean 'CP0C3_IPLV'? > (0x3fU << CP0C6_KPOS) | \ > ^~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:414:49: error: 'CP0C6_KE' undeclared (first use in this function); did you mean 'CP0C4_AE'? > (1U << CP0C6_KE) | \ > ^~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > > > > --- > > target/mips/kvm.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++++++ > > target/mips/machine.c | 6 +- > > 2 files changed, 216 insertions(+), 2 deletions(-) > > > > diff --git a/target/mips/kvm.c b/target/mips/kvm.c > > index de3e26e..96cfa10 100644 > > --- a/target/mips/kvm.c > > +++ b/target/mips/kvm.c > > @@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) > > (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) > > > > #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) > > +#define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) > > #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) > > #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) > > #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) > > +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) > > +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) > > +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) > > +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) > > #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) > > +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) > > #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) > > #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) > > #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) > > @@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) > > #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) > > #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) > > #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) > > +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) > > #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) > > #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) > > #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) > > #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) > > #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) > > #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) > > +#define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) > > +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) > > #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) > > +#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) > > +#define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) > > +#define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) > > +#define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) > > +#define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) > > +#define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) > > > > static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, > > int32_t *addr) > > @@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, > > (1U << CP0C5_UFE) | \ > > (1U << CP0C5_FRE) | \ > > (1U << CP0C5_UFR)) > > +#define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > > + (0x3fU << CP0C6_KPOS) | \ > > + (1U << CP0C6_KE) | \ > > + (1U << CP0C6_VTLBONLY) | \ > > + (1U << CP0C6_LASX) | \ > > + (1U << CP0C6_SSEN) | \ > > + (1U << CP0C6_DISDRTIME) | \ > > + (1U << CP0C6_PIXNUEN) | \ > > + (1U << CP0C6_SCRAND) | \ > > + (1U << CP0C6_LLEXCEN) | \ > > + (1U << CP0C6_DISVC) | \ > > + (1U << CP0C6_VCLRU) | \ > > + (1U << CP0C6_DCLRU) | \ > > + (1U << CP0C6_PIXUEN) | \ > > + (1U << CP0C6_DISBLKLYEN) | \ > > + (1U << CP0C6_UMEMUALEN) | \ > > + (1U << CP0C6_SFBEN) | \ > > + (1U << CP0C6_FLTINT) | \ > > + (1U << CP0C6_VLTINT) | \ > > + (1U << CP0C6_DISBTB) | \ > > + (3U << CP0C6_STPREFCTL) | \ > > + (1U << CP0C6_INSTPREF) | \ > > + (1U << CP0C6_DATAPREF)) > > It seems a lot of the defines here aren't in this commit. Was one missed? > > -- > Alex Bennée [-- Attachment #2: Type: text/html, Size: 11317 bytes --] ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PULL 4/6] target/mips: Add more CP0 register for save/restore 2020-06-11 9:50 ` Alex Bennée 2020-06-11 10:00 ` Aleksandar Markovic 2020-06-11 10:58 ` Aleksandar Markovic @ 2020-06-11 18:36 ` Aleksandar Markovic 2 siblings, 0 replies; 14+ messages in thread From: Aleksandar Markovic @ 2020-06-11 18:36 UTC (permalink / raw) To: Alex Bennée; +Cc: Peter Maydell, QEMU Developers чет, 11. јун 2020. у 11:50 Alex Bennée <alex.bennee@linaro.org> је написао/ла: > > > Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> writes: > > > From: Huacai Chen <zltjiangshi@gmail.com> > > > > Add more CP0 register for save/restore, including: EBase, XContext, > > PageGrain, PWBase, PWSize, PWField, PWCtl, Config*, KScratch1~KScratch6. > > > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > > Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > > Message-Id: <1588501221-1205-6-git-send-email-chenhc@lemote.com> > > It seems while our mips cross build has been broken this commit has > caused a build regression: > Alex, this problem should disappear now, since a commit that is supposed to fix it is upstreamed this afternoon. From my side, I will expand my test bed for similar cases that require more thorough attention. Could you just please confirm or disconfirm that your scenario does not have this problem anymore? Thanks, Aleksandar > make docker-test-build@debian-mips-cross J=30 > > Results in: > > /tmp/qemu-test/src/target/mips/kvm.c: In function 'kvm_mips_put_cp0_registers': > /tmp/qemu-test/src/target/mips/kvm.c:412:49: error: 'CP0C6_BPPASS' undeclared (first use in this function); did you mean 'CP0C3_LPA'? > #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > ^~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:412:49: note: each undeclared identifier is reported only once for each function it appears in > #define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > ^~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:413:52: error: 'CP0C6_KPOS' undeclared (first use in this function); did you mean 'CP0C3_IPLV'? > (0x3fU << CP0C6_KPOS) | \ > ^~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:414:49: error: 'CP0C6_KE' undeclared (first use in this function); did you mean 'CP0C4_AE'? > (1U << CP0C6_KE) | \ > ^~~~~~~~ > /tmp/qemu-test/src/target/mips/kvm.c:923:35: note: in expansion of macro 'KVM_REG_MIPS_CP0_CONFIG6_MASK' > KVM_REG_MIPS_CP0_CONFIG6_MASK); > > > > --- > > target/mips/kvm.c | 212 ++++++++++++++++++++++++++++++++++++++++++++++++++ > > target/mips/machine.c | 6 +- > > 2 files changed, 216 insertions(+), 2 deletions(-) > > > > diff --git a/target/mips/kvm.c b/target/mips/kvm.c > > index de3e26e..96cfa10 100644 > > --- a/target/mips/kvm.c > > +++ b/target/mips/kvm.c > > @@ -245,10 +245,16 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) > > (KVM_REG_MIPS_CP0 | KVM_REG_SIZE_U64 | (8 * (_R) + (_S))) > > > > #define KVM_REG_MIPS_CP0_INDEX MIPS_CP0_32(0, 0) > > +#define KVM_REG_MIPS_CP0_RANDOM MIPS_CP0_32(1, 0) > > #define KVM_REG_MIPS_CP0_CONTEXT MIPS_CP0_64(4, 0) > > #define KVM_REG_MIPS_CP0_USERLOCAL MIPS_CP0_64(4, 2) > > #define KVM_REG_MIPS_CP0_PAGEMASK MIPS_CP0_32(5, 0) > > +#define KVM_REG_MIPS_CP0_PAGEGRAIN MIPS_CP0_32(5, 1) > > +#define KVM_REG_MIPS_CP0_PWBASE MIPS_CP0_64(5, 5) > > +#define KVM_REG_MIPS_CP0_PWFIELD MIPS_CP0_64(5, 6) > > +#define KVM_REG_MIPS_CP0_PWSIZE MIPS_CP0_64(5, 7) > > #define KVM_REG_MIPS_CP0_WIRED MIPS_CP0_32(6, 0) > > +#define KVM_REG_MIPS_CP0_PWCTL MIPS_CP0_32(6, 6) > > #define KVM_REG_MIPS_CP0_HWRENA MIPS_CP0_32(7, 0) > > #define KVM_REG_MIPS_CP0_BADVADDR MIPS_CP0_64(8, 0) > > #define KVM_REG_MIPS_CP0_COUNT MIPS_CP0_32(9, 0) > > @@ -258,13 +264,22 @@ int kvm_mips_set_ipi_interrupt(MIPSCPU *cpu, int irq, int level) > > #define KVM_REG_MIPS_CP0_CAUSE MIPS_CP0_32(13, 0) > > #define KVM_REG_MIPS_CP0_EPC MIPS_CP0_64(14, 0) > > #define KVM_REG_MIPS_CP0_PRID MIPS_CP0_32(15, 0) > > +#define KVM_REG_MIPS_CP0_EBASE MIPS_CP0_64(15, 1) > > #define KVM_REG_MIPS_CP0_CONFIG MIPS_CP0_32(16, 0) > > #define KVM_REG_MIPS_CP0_CONFIG1 MIPS_CP0_32(16, 1) > > #define KVM_REG_MIPS_CP0_CONFIG2 MIPS_CP0_32(16, 2) > > #define KVM_REG_MIPS_CP0_CONFIG3 MIPS_CP0_32(16, 3) > > #define KVM_REG_MIPS_CP0_CONFIG4 MIPS_CP0_32(16, 4) > > #define KVM_REG_MIPS_CP0_CONFIG5 MIPS_CP0_32(16, 5) > > +#define KVM_REG_MIPS_CP0_CONFIG6 MIPS_CP0_32(16, 6) > > +#define KVM_REG_MIPS_CP0_XCONTEXT MIPS_CP0_64(20, 0) > > #define KVM_REG_MIPS_CP0_ERROREPC MIPS_CP0_64(30, 0) > > +#define KVM_REG_MIPS_CP0_KSCRATCH1 MIPS_CP0_64(31, 2) > > +#define KVM_REG_MIPS_CP0_KSCRATCH2 MIPS_CP0_64(31, 3) > > +#define KVM_REG_MIPS_CP0_KSCRATCH3 MIPS_CP0_64(31, 4) > > +#define KVM_REG_MIPS_CP0_KSCRATCH4 MIPS_CP0_64(31, 5) > > +#define KVM_REG_MIPS_CP0_KSCRATCH5 MIPS_CP0_64(31, 6) > > +#define KVM_REG_MIPS_CP0_KSCRATCH6 MIPS_CP0_64(31, 7) > > > > static inline int kvm_mips_put_one_reg(CPUState *cs, uint64_t reg_id, > > int32_t *addr) > > @@ -394,6 +409,29 @@ static inline int kvm_mips_get_one_ureg64(CPUState *cs, uint64_t reg_id, > > (1U << CP0C5_UFE) | \ > > (1U << CP0C5_FRE) | \ > > (1U << CP0C5_UFR)) > > +#define KVM_REG_MIPS_CP0_CONFIG6_MASK ((1U << CP0C6_BPPASS) | \ > > + (0x3fU << CP0C6_KPOS) | \ > > + (1U << CP0C6_KE) | \ > > + (1U << CP0C6_VTLBONLY) | \ > > + (1U << CP0C6_LASX) | \ > > + (1U << CP0C6_SSEN) | \ > > + (1U << CP0C6_DISDRTIME) | \ > > + (1U << CP0C6_PIXNUEN) | \ > > + (1U << CP0C6_SCRAND) | \ > > + (1U << CP0C6_LLEXCEN) | \ > > + (1U << CP0C6_DISVC) | \ > > + (1U << CP0C6_VCLRU) | \ > > + (1U << CP0C6_DCLRU) | \ > > + (1U << CP0C6_PIXUEN) | \ > > + (1U << CP0C6_DISBLKLYEN) | \ > > + (1U << CP0C6_UMEMUALEN) | \ > > + (1U << CP0C6_SFBEN) | \ > > + (1U << CP0C6_FLTINT) | \ > > + (1U << CP0C6_VLTINT) | \ > > + (1U << CP0C6_DISBTB) | \ > > + (3U << CP0C6_STPREFCTL) | \ > > + (1U << CP0C6_INSTPREF) | \ > > + (1U << CP0C6_DATAPREF)) > > It seems a lot of the defines here aren't in this commit. Was one missed? > > -- > Alex Bennée ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-06-11 18:37 UTC | newest] Thread overview: 14+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2020-06-01 12:18 [PULL 0/6] MIPS queue for June 1st, 2020 Aleksandar Markovic 2020-06-01 12:18 ` [PULL 1/6] tests/Makefile: Fix description of "make check" Aleksandar Markovic 2020-06-01 12:18 ` [PULL 2/6] configure: Add KVM target support for MIPS64 Aleksandar Markovic 2020-06-01 12:18 ` [PULL 3/6] hw/mips: Add CPU IRQ3 delivery for KVM Aleksandar Markovic 2020-06-01 12:18 ` [PULL 4/6] target/mips: Add more CP0 register for save/restore Aleksandar Markovic 2020-06-01 12:18 ` [PULL 5/6] target/mips: Support variable page size Aleksandar Markovic 2020-06-01 12:18 ` [PULL 6/6] hw/mips: fuloong2e: Set preferred page size to 16KB Aleksandar Markovic 2020-06-01 12:20 ` [PULL 0/6] MIPS queue for June 1st, 2020 Peter Maydell 2020-06-01 12:45 ` Aleksandar Markovic -- strict thread matches above, loose matches on Subject: below -- 2020-06-01 12:43 Aleksandar Markovic 2020-06-01 12:43 ` [PULL 4/6] target/mips: Add more CP0 register for save/restore Aleksandar Markovic 2020-06-11 9:50 ` Alex Bennée 2020-06-11 10:00 ` Aleksandar Markovic 2020-06-11 10:58 ` Aleksandar Markovic 2020-06-11 18:36 ` Aleksandar Markovic
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