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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id b19sm7292575pft.74.2020.06.08.07.18.15 (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 08 Jun 2020 07:18:16 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Date: Mon, 8 Jun 2020 07:17:29 -0700 Message-Id: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x532.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng This series updates the 'sifive_u' machine support: - Add GPIO controller support - Support reboot functionality via GPIO pin#10 - Change SiFive E/U series CPU reset vector to 0x1004 - Support Mode Select (MSEL[3:0]) settings at 0x1000 via a new "msel" machine property - Add a dummy DDR memory controller device The series also does some clean-ups to the existing codes. With this series, QEMU can boot U-Boot SPL built for SiFive FU540 all the way up to loading U-Boot proper from MMC: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -m 8G -bios u-boot-spl.bin U-Boot SPL 2020.07-rc3-00208-g88bd5b1 (Jun 08 2020 - 20:16:10 +0800) Trying to boot from MMC1 Unhandled exception: Load access fault EPC: 0000000008009be6 TVAL: 0000000010050014 The last big gap for the 'sifive_u' machine is the QSPI modeling. Bin Meng (15): hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit hw/riscv: sifive_u: Generate device tree node for OTP hw/riscv: sifive_gpio: Clean up the codes hw/riscv: sifive_gpio: Add a new 'ngpio' property hw/riscv: sifive_u: Hook a GPIO controller hw/riscv: sifive_gpio: Do not blindly trigger output IRQs hw/riscv: sifive_u: Add reset functionality hw/riscv: sifive_u: Rename serial property get/set functions to a generic name hw/riscv: sifive_u: Add a new property msel for MSEL pin state hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv/opentitan.c | 29 ++++---- hw/riscv/sifive_e.c | 32 +++++---- hw/riscv/sifive_gpio.c | 45 +++++++----- hw/riscv/sifive_u.c | 158 ++++++++++++++++++++++++++++++++++------- include/hw/riscv/sifive_gpio.h | 8 ++- include/hw/riscv/sifive_u.h | 27 +++++++ target/riscv/cpu.c | 4 +- 7 files changed, 223 insertions(+), 80 deletions(-) -- 2.7.4