From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state
Date: Mon, 8 Jun 2020 07:17:42 -0700 [thread overview]
Message-ID: <1591625864-31494-14-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
SiFive FU540 SoC supports booting from several sources, which are
controlled using the Mode Select (MSEL[3:0]) pins on the chip.
Typically, the boot process runs through several stages before it
begins execution of user-provided programs.
The SoC supports booting from memory-mapped QSPI flash, which is
how start_in_flash property is used for at present. This matches
MSEL = 1 configuration (QSPI0).
Typical booting flows involve the Zeroth Stage Boot Loader (ZSBL).
It's not necessary for QEMU to implement the full ZSBL ROM codes,
because we know ZSBL downloads the next stage program into the L2
LIM at address 0x8000000 and executes from there. We can bypass
the whole ZSBL execution and use "-bios" to load the next stage
program directly if MSEL indicates a ZSBL booting flow.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 39 +++++++++++++++++++++++++++++++--------
include/hw/riscv/sifive_u.h | 6 ++++++
2 files changed, 37 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 0a86ffc..f64aa52 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -408,8 +408,34 @@ static void sifive_u_machine_init(MachineState *machine)
/* create device tree */
create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
- riscv_find_and_load_firmware(machine, BIOS_FILENAME,
- memmap[SIFIVE_U_DRAM].base, NULL);
+ if (s->start_in_flash) {
+ /*
+ * If start_in_flash property is given, assign s->msel to a value
+ * that representing booting from QSPI0 memory-mapped flash.
+ *
+ * This also means that when both start_in_flash and msel properties
+ * are given, start_in_flash takes the precedence over msel.
+ *
+ * Note this is to keep backward compatibility not to break existing
+ * users that use start_in_flash property.
+ */
+ s->msel = MSEL_MEMMAP_QSPI0_FLASH;
+ }
+
+ switch (s->msel) {
+ case MSEL_MEMMAP_QSPI0_FLASH:
+ start_addr = memmap[SIFIVE_U_FLASH0].base;
+ break;
+ case MSEL_L2LIM_QSPI0_FLASH:
+ case MSEL_L2LIM_QSPI2_SD:
+ start_addr = memmap[SIFIVE_U_L2LIM].base;
+ break;
+ default:
+ start_addr = memmap[SIFIVE_U_DRAM].base;
+ break;
+ }
+
+ riscv_find_and_load_firmware(machine, BIOS_FILENAME, start_addr, NULL);
if (machine->kernel_filename) {
uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename,
@@ -427,13 +453,9 @@ static void sifive_u_machine_init(MachineState *machine)
}
}
- if (s->start_in_flash) {
- start_addr = memmap[SIFIVE_U_FLASH0].base;
- }
-
/* reset vector */
uint32_t reset_vec[8] = {
- 0x00000000,
+ s->msel, /* MSEL pin state */
0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
0x01c28593, /* addi a1, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
@@ -505,7 +527,8 @@ static void sifive_u_machine_instance_init(Object *obj)
sifive_u_machine_set_start_in_flash);
object_property_set_description(obj, "start-in-flash",
"Set on to tell QEMU's ROM to jump to "
- "flash. Otherwise QEMU will jump to DRAM");
+ "flash. Otherwise QEMU will jump to DRAM "
+ "or L2LIM depending on the msel value");
s->msel = 0;
object_property_add(obj, "msel", "uint32",
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index d82cfe0..5d80f91 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -111,6 +111,12 @@ enum {
SIFIVE_U_RTCCLK_FREQ = 1000000
};
+enum {
+ MSEL_MEMMAP_QSPI0_FLASH = 1,
+ MSEL_L2LIM_QSPI0_FLASH = 6,
+ MSEL_L2LIM_QSPI2_SD = 11
+};
+
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
#define SIFIVE_U_COMPUTE_CPU_COUNT 4
--
2.7.4
next prev parent reply other threads:[~2020-06-08 14:28 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
2020-06-15 16:05 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
2020-06-15 16:06 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Bin Meng
2020-06-15 16:07 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Bin Meng
2020-06-15 16:08 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Bin Meng
2020-06-15 16:13 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
2020-06-15 16:16 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
2020-06-15 16:26 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
2020-06-15 16:28 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
2020-06-15 16:35 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
2020-06-15 16:39 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
2020-06-15 16:41 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
2020-06-15 19:02 ` Alistair Francis
2020-06-08 14:17 ` Bin Meng [this message]
2020-06-15 19:04 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Alistair Francis
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-15 19:20 ` Alistair Francis
2020-06-15 19:31 ` [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Alistair Francis
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