From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
Date: Mon, 8 Jun 2020 07:17:32 -0700 [thread overview]
Message-ID: <1591625864-31494-4-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
There is no need to retrieve all PLIC IRQ information in order to
just connect the GEM IRQ. Use qdev_get_gpio_in() directly like
what is done for other peripherals.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f9fef2b..cf7f833 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -528,7 +528,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
- qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES];
char *plic_hart_config;
size_t plic_hart_config_len;
int i;
@@ -612,10 +611,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
object_property_set_bool(OBJECT(&s->otp), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
- for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) {
- plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i);
- }
-
if (nd->used) {
qemu_check_nic_model(nd, TYPE_CADENCE_GEM);
qdev_set_nic_properties(DEVICE(&s->gem), nd);
@@ -629,7 +624,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
- plic_gpios[SIFIVE_U_GEM_IRQ]);
+ qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
--
2.7.4
next prev parent reply other threads:[~2020-06-08 14:21 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
2020-06-15 16:05 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
2020-06-15 16:06 ` Alistair Francis
2020-06-08 14:17 ` Bin Meng [this message]
2020-06-15 16:07 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Alistair Francis
2020-06-08 14:17 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Bin Meng
2020-06-15 16:08 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Bin Meng
2020-06-15 16:13 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
2020-06-15 16:16 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
2020-06-15 16:26 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
2020-06-15 16:28 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
2020-06-15 16:35 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
2020-06-15 16:39 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
2020-06-15 16:41 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
2020-06-15 19:02 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-15 19:20 ` Alistair Francis
2020-06-15 19:31 ` [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Alistair Francis
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