From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP
Date: Mon, 8 Jun 2020 07:17:33 -0700 [thread overview]
Message-ID: <1591625864-31494-5-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
Upstream U-Boot v2020.07 codes switch to access SiFive FU540 OTP
based on device tree information. Let's generate the device tree
node for OTP.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index cf7f833..8dc6842 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -207,6 +207,17 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
+ nodename = g_strdup_printf("/soc/otp@%lx",
+ (long)memmap[SIFIVE_U_OTP].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_OTP].base,
+ 0x0, memmap[SIFIVE_U_OTP].size);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "sifive,fu540-c000-otp");
+ g_free(nodename);
+
prci_phandle = phandle++;
nodename = g_strdup_printf("/soc/clock-controller@%lx",
(long)memmap[SIFIVE_U_PRCI].base);
--
2.7.4
next prev parent reply other threads:[~2020-06-08 14:22 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
2020-06-15 16:05 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
2020-06-15 16:06 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Bin Meng
2020-06-15 16:07 ` Alistair Francis
2020-06-08 14:17 ` Bin Meng [this message]
2020-06-15 16:08 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Alistair Francis
2020-06-08 14:17 ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Bin Meng
2020-06-15 16:13 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
2020-06-15 16:16 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
2020-06-15 16:26 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
2020-06-15 16:28 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
2020-06-15 16:35 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
2020-06-15 16:39 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
2020-06-15 16:41 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
2020-06-15 19:02 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
2020-06-15 19:04 ` Alistair Francis
2020-06-08 14:17 ` [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-15 19:20 ` Alistair Francis
2020-06-15 19:31 ` [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Alistair Francis
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