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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes
Date: Mon,  8 Jun 2020 07:17:34 -0700	[thread overview]
Message-ID: <1591625864-31494-6-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1591625864-31494-1-git-send-email-bmeng.cn@gmail.com>

From: Bin Meng <bin.meng@windriver.com>

Do various minor clean-ups to the exisiting codes for:

- coding convention conformance
- remove unnecessary blank lines
- spell SiFive correctly

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 hw/riscv/sifive_gpio.c         | 13 +++++--------
 include/hw/riscv/sifive_gpio.h |  7 ++++---
 2 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c
index 5c7c596..c9cffa2 100644
--- a/hw/riscv/sifive_gpio.c
+++ b/hw/riscv/sifive_gpio.c
@@ -1,5 +1,5 @@
 /*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
  *
  * Copyright 2019 AdaCore
  *
@@ -20,7 +20,6 @@
 
 static void update_output_irq(SIFIVEGPIOState *s)
 {
-
     uint32_t pending;
     uint32_t pin;
 
@@ -186,7 +185,7 @@ static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size)
 }
 
 static void sifive_gpio_write(void *opaque, hwaddr offset,
-                       uint64_t value, unsigned int size)
+                              uint64_t value, unsigned int size)
 {
     SIFIVEGPIOState *s = SIFIVE_GPIO(opaque);
 
@@ -318,7 +317,6 @@ static void sifive_gpio_reset(DeviceState *dev)
     s->out_xor = 0;
     s->in = 0;
     s->in_mask = 0;
-
 }
 
 static const VMStateDescription vmstate_sifive_gpio = {
@@ -342,8 +340,8 @@ static const VMStateDescription vmstate_sifive_gpio = {
         VMSTATE_UINT32(iof_en,    SIFIVEGPIOState),
         VMSTATE_UINT32(iof_sel,   SIFIVEGPIOState),
         VMSTATE_UINT32(out_xor,   SIFIVEGPIOState),
-        VMSTATE_UINT32(in, SIFIVEGPIOState),
-        VMSTATE_UINT32(in_mask, SIFIVEGPIOState),
+        VMSTATE_UINT32(in,        SIFIVEGPIOState),
+        VMSTATE_UINT32(in_mask,   SIFIVEGPIOState),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -356,7 +354,6 @@ static void sifive_gpio_init(Object *obj)
             TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE);
     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 
-
     for (int i = 0; i < SIFIVE_GPIO_PINS; i++) {
         sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]);
     }
@@ -371,7 +368,7 @@ static void sifive_gpio_class_init(ObjectClass *klass, void *data)
 
     dc->vmsd = &vmstate_sifive_gpio;
     dc->reset = sifive_gpio_reset;
-    dc->desc = "sifive GPIO";
+    dc->desc = "SiFive GPIO";
 }
 
 static const TypeInfo sifive_gpio_info = {
diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h
index fce03d6..ad915b2 100644
--- a/include/hw/riscv/sifive_gpio.h
+++ b/include/hw/riscv/sifive_gpio.h
@@ -1,5 +1,5 @@
 /*
- * sifive System-on-Chip general purpose input/output register definition
+ * SiFive System-on-Chip general purpose input/output register definition
  *
  * Copyright 2019 AdaCore
  *
@@ -10,10 +10,12 @@
  * This code is licensed under the GPL version 2 or later.  See
  * the COPYING file in the top-level directory.
  */
+
 #ifndef SIFIVE_GPIO_H
 #define SIFIVE_GPIO_H
 
 #include "hw/sysbus.h"
+
 #define TYPE_SIFIVE_GPIO "sifive_soc.gpio"
 #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_GPIO)
 
@@ -66,7 +68,6 @@ typedef struct SIFIVEGPIOState {
     uint32_t out_xor;
     uint32_t in;
     uint32_t in_mask;
-
 } SIFIVEGPIOState;
 
-#endif
+#endif /* SIFIVE_GPIO_H */
-- 
2.7.4



  parent reply	other threads:[~2020-06-08 14:23 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-08 14:17 [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Bin Meng
2020-06-08 14:17 ` [PATCH 01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions Bin Meng
2020-06-15 16:05   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 02/15] hw/riscv: opentitan: " Bin Meng
2020-06-15 16:06   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit Bin Meng
2020-06-15 16:07   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 04/15] hw/riscv: sifive_u: Generate device tree node for OTP Bin Meng
2020-06-15 16:08   ` Alistair Francis
2020-06-08 14:17 ` Bin Meng [this message]
2020-06-15 16:13   ` [PATCH 05/15] hw/riscv: sifive_gpio: Clean up the codes Alistair Francis
2020-06-08 14:17 ` [PATCH 06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property Bin Meng
2020-06-15 16:16   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 07/15] hw/riscv: sifive_u: Hook a GPIO controller Bin Meng
2020-06-15 16:26   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs Bin Meng
2020-06-15 16:28   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 09/15] hw/riscv: sifive_u: Add reset functionality Bin Meng
2020-06-15 16:35   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name Bin Meng
2020-06-15 16:39   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state Bin Meng
2020-06-15 16:41   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
2020-06-15 19:02   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
2020-06-15 19:04   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
2020-06-15 19:04   ` Alistair Francis
2020-06-08 14:17 ` [PATCH 15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-15 19:20   ` Alistair Francis
2020-06-15 19:31 ` [PATCH 00/15] hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support Alistair Francis

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