From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>
Subject: [PATCH v2 1/5] target/riscv: Rename IBEX CPU init routine
Date: Mon, 15 Jun 2020 17:50:37 -0700 [thread overview]
Message-ID: <1592268641-7478-2-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1592268641-7478-1-git-send-email-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
Current IBEX CPU init routine name seems to be too generic.
Since it uses a different reset vector from the generic one,
it merits a dedicated name.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Changes in v2:
- new patch: Rename IBEX CPU init routine
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e867766..5f03458 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -153,7 +153,7 @@ static void rvxx_imacu_nommu_cpu_init(Object *obj)
#if defined(TARGET_RISCV32)
-static void rv32_imcu_nommu_cpu_init(Object *obj)
+static void rv32_ibex_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
set_misa(env, RV32 | RVI | RVM | RVC | RVU);
@@ -577,7 +577,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init),
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_imcu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init),
--
2.7.4
next prev parent reply other threads:[~2020-06-16 0:51 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-16 0:50 [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support Bin Meng
2020-06-16 0:50 ` Bin Meng [this message]
2020-06-16 17:07 ` [PATCH v2 1/5] target/riscv: Rename IBEX CPU init routine Alistair Francis
2020-06-16 0:50 ` [PATCH v2 2/5] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Bin Meng
2020-06-16 17:09 ` Alistair Francis
2020-06-17 16:30 ` Alistair Francis
2020-06-18 0:41 ` Bin Meng
2020-06-18 5:08 ` Bin Meng
2020-06-19 6:04 ` Alistair Francis
2020-06-16 0:50 ` [PATCH v2 3/5] hw/riscv: sifive_u: Support different boot source per MSEL pin state Bin Meng
2020-06-16 0:50 ` [PATCH v2 4/5] hw/riscv: sifive_u: Sort the SoC memmap table entries Bin Meng
2020-06-16 0:50 ` [PATCH v2 5/5] hw/riscv: sifive_u: Add a dummy DDR memory controller device Bin Meng
2020-06-16 20:23 ` [PATCH v2 0/5] hw/riscv: sifive_u: Add Mode Select (MSEL[3:0]) support Alistair Francis
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