* [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000
@ 2020-07-09 1:09 Bin Meng
2020-07-09 1:09 ` [PATCH 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU Bin Meng
2020-07-09 5:15 ` [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000 Philippe Mathieu-Daudé
0 siblings, 2 replies; 4+ messages in thread
From: Bin Meng @ 2020-07-09 1:09 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x10000.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index dc46f64..3413369 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -70,7 +70,7 @@ static const struct MemmapEntry {
hwaddr size;
} sifive_u_memmap[] = {
[SIFIVE_U_DEBUG] = { 0x0, 0x100 },
- [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
+ [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index a187aa3..ea4be98 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -57,7 +57,7 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} spike_memmap[] = {
- [SPIKE_MROM] = { 0x1000, 0x11000 },
+ [SPIKE_MROM] = { 0x1000, 0xf000 },
[SPIKE_CLINT] = { 0x2000000, 0x10000 },
[SPIKE_DRAM] = { 0x80000000, 0x0 },
};
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 5ca49c5..37b8c55 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -53,7 +53,7 @@ static const struct MemmapEntry {
hwaddr size;
} virt_memmap[] = {
[VIRT_DEBUG] = { 0x0, 0x100 },
- [VIRT_MROM] = { 0x1000, 0x11000 },
+ [VIRT_MROM] = { 0x1000, 0xf000 },
[VIRT_TEST] = { 0x100000, 0x1000 },
[VIRT_RTC] = { 0x101000, 0x1000 },
[VIRT_CLINT] = { 0x2000000, 0x10000 },
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU
2020-07-09 1:09 [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000 Bin Meng
@ 2020-07-09 1:09 ` Bin Meng
2020-07-09 5:15 ` [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000 Philippe Mathieu-Daudé
1 sibling, 0 replies; 4+ messages in thread
From: Bin Meng @ 2020-07-09 1:09 UTC (permalink / raw)
To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
The reset vector codes are subject to change, e.g.: with recent
fw_dynamic type image support, it breaks oreboot again.
Add a subregion in the MROM, with the size of machine RAM stored,
so that we can provide a reliable way for bootloader to detect
whether it is running in QEMU.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/sifive_u.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3413369..6d714a2 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -88,6 +88,7 @@ static const struct MemmapEntry {
#define OTP_SERIAL 1
#define GEM_REVISION 0x10070109
+#define MROM_RAMSIZE_OFFSET 0xf8
static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
uint64_t mem_size, const char *cmdline)
@@ -382,6 +383,7 @@ static void sifive_u_machine_init(MachineState *machine)
int i;
uint32_t fdt_load_addr;
uint64_t kernel_entry;
+ ram_addr_t ram_size = machine->ram_size;
/* Initialize SoC */
object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC);
@@ -391,7 +393,7 @@ static void sifive_u_machine_init(MachineState *machine)
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
- machine->ram_size, &error_fatal);
+ ram_size, &error_fatal);
memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
main_mem);
@@ -406,7 +408,7 @@ static void sifive_u_machine_init(MachineState *machine)
qemu_allocate_irq(sifive_u_machine_reset, NULL, 0));
/* create device tree */
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
+ create_fdt(s, memmap, ram_size, machine->kernel_cmdline);
if (s->start_in_flash) {
/*
@@ -443,7 +445,7 @@ static void sifive_u_machine_init(MachineState *machine)
if (machine->initrd_filename) {
hwaddr start;
hwaddr end = riscv_load_initrd(machine->initrd_filename,
- machine->ram_size, kernel_entry,
+ ram_size, kernel_entry,
&start);
qemu_fdt_setprop_cell(s->fdt, "/chosen",
"linux,initrd-start", start);
@@ -460,7 +462,7 @@ static void sifive_u_machine_init(MachineState *machine)
/* Compute the fdt load address in dram */
fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
- machine->ram_size, s->fdt);
+ ram_size, s->fdt);
#if defined(TARGET_RISCV64)
start_addr_hi32 = start_addr >> 32;
#endif
@@ -496,6 +498,17 @@ static void sifive_u_machine_init(MachineState *machine)
riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
memmap[SIFIVE_U_MROM].size,
sizeof(reset_vec), kernel_entry);
+
+ /*
+ * Tell guest the machine ram size at MROM_RAMSIZE_OFFSET.
+ * On real hardware, the 64-bit value from MROM_RAMSIZE_OFFSET is zero.
+ * QEMU aware bootloader (e.g.: oreboot, U-Boot) can check value stored
+ * here to determine whether it is running in QEMU.
+ */
+ ram_size = cpu_to_le32(ram_size);
+ rom_add_blob_fixed_as("mrom.ram_size", &ram_size, sizeof(ram_size),
+ memmap[SIFIVE_U_MROM].base + MROM_RAMSIZE_OFFSET,
+ &address_space_memory);
}
static bool sifive_u_machine_get_start_in_flash(Object *obj, Error **errp)
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000
2020-07-09 1:09 [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000 Bin Meng
2020-07-09 1:09 ` [PATCH 2/2] hw/riscv: sifive_u: Provide a reliable way for bootloader to detect whether it is running in QEMU Bin Meng
@ 2020-07-09 5:15 ` Philippe Mathieu-Daudé
2020-07-09 10:03 ` Bin Meng
1 sibling, 1 reply; 4+ messages in thread
From: Philippe Mathieu-Daudé @ 2020-07-09 5:15 UTC (permalink / raw)
To: Bin Meng, Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
Sagar Karandikar, qemu-devel, qemu-riscv
Cc: Bin Meng
On 7/9/20 3:09 AM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
>
> At present the size of Mask ROM for sifive_u / spike / virt machines
> is set to 0x11000, which ends at an unusual address. This changes the
> size to 0xf000 so that it ends at 0x10000.
Maybe the size is correct but the first 4K are shadowed by the DEBUG
region?
Anyway for QEMU this patch is an improvement, so:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> hw/riscv/sifive_u.c | 2 +-
> hw/riscv/spike.c | 2 +-
> hw/riscv/virt.c | 2 +-
> 3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index dc46f64..3413369 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -70,7 +70,7 @@ static const struct MemmapEntry {
> hwaddr size;
> } sifive_u_memmap[] = {
> [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
> - [SIFIVE_U_MROM] = { 0x1000, 0x11000 },
> + [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
> [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
> [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
> [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
> index a187aa3..ea4be98 100644
> --- a/hw/riscv/spike.c
> +++ b/hw/riscv/spike.c
> @@ -57,7 +57,7 @@ static const struct MemmapEntry {
> hwaddr base;
> hwaddr size;
> } spike_memmap[] = {
> - [SPIKE_MROM] = { 0x1000, 0x11000 },
> + [SPIKE_MROM] = { 0x1000, 0xf000 },
> [SPIKE_CLINT] = { 0x2000000, 0x10000 },
> [SPIKE_DRAM] = { 0x80000000, 0x0 },
> };
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 5ca49c5..37b8c55 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -53,7 +53,7 @@ static const struct MemmapEntry {
> hwaddr size;
> } virt_memmap[] = {
> [VIRT_DEBUG] = { 0x0, 0x100 },
> - [VIRT_MROM] = { 0x1000, 0x11000 },
> + [VIRT_MROM] = { 0x1000, 0xf000 },
> [VIRT_TEST] = { 0x100000, 0x1000 },
> [VIRT_RTC] = { 0x101000, 0x1000 },
> [VIRT_CLINT] = { 0x2000000, 0x10000 },
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000
2020-07-09 5:15 ` [PATCH 1/2] hw/riscv: Modify MROM size to end at 0x10000 Philippe Mathieu-Daudé
@ 2020-07-09 10:03 ` Bin Meng
0 siblings, 0 replies; 4+ messages in thread
From: Bin Meng @ 2020-07-09 10:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Bin Meng, open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
Hi Philippe,
On Thu, Jul 9, 2020 at 1:15 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
> On 7/9/20 3:09 AM, Bin Meng wrote:
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > At present the size of Mask ROM for sifive_u / spike / virt machines
> > is set to 0x11000, which ends at an unusual address. This changes the
> > size to 0xf000 so that it ends at 0x10000.
>
> Maybe the size is correct but the first 4K are shadowed by the DEBUG
> region?
>
The DEBUG region does not match what the SiFive FU540 manual says. But
we don't support DEBUG in QEMU anyway :)
> Anyway for QEMU this patch is an improvement, so:
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
Thanks for the review!
Regards,
Bin
^ permalink raw reply [flat|nested] 4+ messages in thread
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