From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [PATCH] hw/riscv: sifive_e: Correct debug block size
Date: Thu, 16 Jul 2020 02:30:56 -0700 [thread overview]
Message-ID: <1594891856-15474-1-git-send-email-bmeng.cn@gmail.com> (raw)
Currently the debug region size is set to 0x100, but according to
FE310-G000 and FE310-G002 manuals:
FE310-G000: 0x100 - 0xFFF
FE310-G002: 0x0 - 0xFFF
Change the size to 0x1000 that applies to both.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
hw/riscv/sifive_e.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 7bb97b4..c8b0604 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -54,7 +54,7 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_e_memmap[] = {
- [SIFIVE_E_DEBUG] = { 0x0, 0x100 },
+ [SIFIVE_E_DEBUG] = { 0x0, 0x1000 },
[SIFIVE_E_MROM] = { 0x1000, 0x2000 },
[SIFIVE_E_OTP] = { 0x20000, 0x2000 },
[SIFIVE_E_CLINT] = { 0x2000000, 0x10000 },
--
2.7.4
next reply other threads:[~2020-07-16 9:32 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-16 9:30 Bin Meng [this message]
2020-07-16 9:51 ` [PATCH] hw/riscv: sifive_e: Correct debug block size no-reply
2020-07-21 15:12 ` Alistair Francis
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