From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, riku.voipio@iki.fi, richard.henderson@linaro.org,
laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com,
aleksandar.m.mail@gmail.com
Subject: [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions
Date: Tue, 18 Aug 2020 10:50:43 -0500 [thread overview]
Message-ID: <1597765847-16637-31-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1597765847-16637-1-git-send-email-tsimpson@quicinc.com>
Helpers won't work if there are multiple definitions, so we override these
instructions using #define fGEN_TCG_<tag>.
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 198 +++++++++++++++++++++++++++++++++++++++++++++++
target/hexagon/helper.h | 2 +
target/hexagon/genptr.c | 1 +
3 files changed, 201 insertions(+)
create mode 100644 target/hexagon/gen_tcg.h
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
new file mode 100644
index 0000000..35568d1
--- /dev/null
+++ b/target/hexagon/gen_tcg.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_GEN_TCG_H
+#define HEXAGON_GEN_TCG_H
+
+/*
+ * Here is a primer to understand the tag names for load/store instructions
+ *
+ * Data types
+ * b signed byte r0 = memb(r2+#0)
+ * ub unsigned byte r0 = memub(r2+#0)
+ * h signed half word (16 bits) r0 = memh(r2+#0)
+ * uh unsigned half word r0 = memuh(r2+#0)
+ * i integer (32 bits) r0 = memw(r2+#0)
+ * d double word (64 bits) r1:0 = memd(r2+#0)
+ *
+ * Addressing modes
+ * _io indirect with offset r0 = memw(r1+#4)
+ * _ur absolute with register offset r0 = memw(r1<<#4+##variable)
+ * _rr indirect with register offset r0 = memw(r1+r4<<#2)
+ * gp global pointer relative r0 = memw(gp+#200)
+ * _sp stack pointer relative r0 = memw(r29+#12)
+ * _ap absolute set r0 = memw(r1=##variable)
+ * _pr post increment register r0 = memw(r1++m1)
+ * _pi post increment immediate r0 = memb(r1++#1)
+ */
+
+/* Macros for complex addressing modes */
+#define GET_EA_ap \
+ do { \
+ fEA_IMM(UiV); \
+ tcg_gen_movi_tl(ReV, UiV); \
+ } while (0)
+#define GET_EA_pr \
+ do { \
+ fEA_REG(RxV); \
+ fPM_M(RxV, MuV); \
+ } while (0)
+#define GET_EA_pi \
+ do { \
+ fEA_REG(RxV); \
+ fPM_I(RxV, siV); \
+ } while (0)
+
+
+/* Instructions with multiple definitions */
+#define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \
+ do { \
+ fMUST_IMMEXT(UiV); \
+ fEA_IMM(UiV); \
+ fLOAD(1, SIZE, SIGN, EA, RES); \
+ tcg_gen_movi_tl(ReV, UiV); \
+ } while (0)
+
+#define fGEN_TCG_L4_loadrub_ap(SHORTCODE) \
+ fGEN_TCG_LOAD_AP(RdV, 1, u)
+#define fGEN_TCG_L4_loadrb_ap(SHORTCODE) \
+ fGEN_TCG_LOAD_AP(RdV, 1, s)
+#define fGEN_TCG_L4_loadruh_ap(SHORTCODE) \
+ fGEN_TCG_LOAD_AP(RdV, 2, u)
+#define fGEN_TCG_L4_loadrh_ap(SHORTCODE) \
+ fGEN_TCG_LOAD_AP(RdV, 2, s)
+#define fGEN_TCG_L4_loadri_ap(SHORTCODE) \
+ fGEN_TCG_LOAD_AP(RdV, 4, u)
+#define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \
+ fGEN_TCG_LOAD_AP(RddV, 8, u)
+
+#define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE;
+#define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE;
+#define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE
+#define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE
+
+/*
+ * Predicated loads
+ * Here is a primer to understand the tag names
+ *
+ * Predicate used
+ * t true "old" value if (p0) r0 = memb(r2+#0)
+ * f false "old" value if (!p0) r0 = memb(r2+#0)
+ * tnew true "new" value if (p0.new) r0 = memb(r2+#0)
+ * fnew false "new" value if (!p0.new) r0 = memb(r2+#0)
+ */
+#define fGEN_TCG_PRED_LOAD(GET_EA, PRED, SIZE, SIGN) \
+ do { \
+ TCGv LSB = tcg_temp_local_new(); \
+ TCGLabel *label = gen_new_label(); \
+ GET_EA; \
+ PRED; \
+ PRED_LOAD_CANCEL(LSB, EA); \
+ tcg_gen_movi_tl(RdV, 0); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
+ fLOAD(1, SIZE, SIGN, EA, RdV); \
+ gen_set_label(label); \
+ tcg_temp_free(LSB); \
+ } while (0)
+
+#define fGEN_TCG_L2_ploadrubt_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, u)
+#define fGEN_TCG_L2_ploadrubf_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, u)
+#define fGEN_TCG_L2_ploadrubtnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, u)
+#define fGEN_TCG_L2_ploadrubfnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 1, u)
+#define fGEN_TCG_L2_ploadrbt_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 1, s)
+#define fGEN_TCG_L2_ploadrbf_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 1, s)
+#define fGEN_TCG_L2_ploadrbtnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 1, s)
+#define fGEN_TCG_L2_ploadrbfnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD({ fEA_REG(RxV); fPM_I(RxV, siV); }, \
+ fLSBNEWNOT(PtN), 1, s)
+
+#define fGEN_TCG_L2_ploadruht_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, u)
+#define fGEN_TCG_L2_ploadruhf_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, u)
+#define fGEN_TCG_L2_ploadruhtnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, u)
+#define fGEN_TCG_L2_ploadruhfnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, u)
+#define fGEN_TCG_L2_ploadrht_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 2, s)
+#define fGEN_TCG_L2_ploadrhf_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 2, s)
+#define fGEN_TCG_L2_ploadrhtnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 2, s)
+#define fGEN_TCG_L2_ploadrhfnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 2, s)
+
+#define fGEN_TCG_L2_ploadrit_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLD(PtV), 4, u)
+#define fGEN_TCG_L2_ploadrif_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBOLDNOT(PtV), 4, u)
+#define fGEN_TCG_L2_ploadritnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEW(PtN), 4, u)
+#define fGEN_TCG_L2_ploadrifnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD(GET_EA_pi, fLSBNEWNOT(PtN), 4, u)
+
+/* Predicated loads into a register pair */
+#define fGEN_TCG_PRED_LOAD_PAIR(GET_EA, PRED) \
+ do { \
+ TCGv LSB = tcg_temp_local_new(); \
+ TCGLabel *label = gen_new_label(); \
+ GET_EA; \
+ PRED; \
+ PRED_LOAD_CANCEL(LSB, EA); \
+ tcg_gen_movi_i64(RddV, 0); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, LSB, 0, label); \
+ fLOAD(1, 8, u, EA, RddV); \
+ gen_set_label(label); \
+ tcg_temp_free(LSB); \
+ } while (0)
+
+#define fGEN_TCG_L2_ploadrdt_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLD(PtV))
+#define fGEN_TCG_L2_ploadrdf_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBOLDNOT(PtV))
+#define fGEN_TCG_L2_ploadrdtnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEW(PtN))
+#define fGEN_TCG_L2_ploadrdfnew_pi(SHORTCODE) \
+ fGEN_TCG_PRED_LOAD_PAIR(GET_EA_pi, fLSBNEWNOT(PtN))
+
+/* load-locked and store-locked */
+#define fGEN_TCG_L2_loadw_locked(SHORTCODE) \
+ SHORTCODE
+#define fGEN_TCG_L4_loadd_locked(SHORTCODE) \
+ SHORTCODE
+#define fGEN_TCG_S2_storew_locked(SHORTCODE) \
+ do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
+#define fGEN_TCG_S4_stored_locked(SHORTCODE) \
+ do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
+
+#endif
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 48b1917..cee902b 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -15,6 +15,8 @@
* along with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#include "gen_tcg.h"
+
DEF_HELPER_2(raise_exception, noreturn, env, i32)
DEF_HELPER_1(debug_start_packet, void, env)
DEF_HELPER_3(debug_check_store_width, void, env, int, int)
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index a85fc14..1808660 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -26,6 +26,7 @@
#include "translate.h"
#include "macros.h"
#include "genptr_helpers.h"
+#include "gen_tcg.h"
#define DEF_TCG_FUNC(TAG, GENFN) \
static void generate_##TAG(CPUHexagonState *env, DisasContext *ctx, \
--
2.7.4
next prev parent reply other threads:[~2020-08-18 16:17 UTC|newest]
Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-18 15:50 [RFC PATCH v3 00/34] Hexagon patch series Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 01/34] Hexagon Update MAINTAINERS file Taylor Simpson
2020-08-26 1:55 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 02/34] Hexagon (target/hexagon) README Taylor Simpson
2020-08-26 2:06 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 03/34] Hexagon (include/elf.h) ELF machine definition Taylor Simpson
2020-08-26 2:06 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 04/34] Hexagon (target/hexagon) scalar core definition Taylor Simpson
2020-08-26 13:35 ` Richard Henderson
2020-08-26 23:51 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 05/34] Hexagon (target/hexagon) register names Taylor Simpson
2020-08-26 13:39 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 06/34] Hexagon (disas) disassembler Taylor Simpson
2020-08-26 13:52 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 07/34] Hexagon (target/hexagon) scalar core helpers Taylor Simpson
2020-08-26 14:16 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 08/34] Hexagon (target/hexagon) GDB Stub Taylor Simpson
2020-08-26 14:17 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 09/34] Hexagon (target/hexagon) architecture types Taylor Simpson
2020-08-26 14:19 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 10/34] Hexagon (target/hexagon) instruction and packet types Taylor Simpson
2020-08-26 14:22 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 11/34] Hexagon (target/hexagon) register fields Taylor Simpson
2020-08-26 14:29 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 12/34] Hexagon (target/hexagon) instruction attributes Taylor Simpson
2020-08-26 14:34 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 13/34] Hexagon (target/hexagon) register map Taylor Simpson
2020-08-26 14:36 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 14/34] Hexagon (target/hexagon) instruction/packet decode Taylor Simpson
2020-08-26 15:06 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 15/34] Hexagon (target/hexagon) instruction printing Taylor Simpson
2020-08-26 15:08 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 16/34] Hexagon (target/hexagon) utility functions Taylor Simpson
2020-08-26 15:10 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 17/34] Hexagon (target/hexagon/imported) arch import - macro definitions Taylor Simpson
2020-08-26 15:17 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 18/34] Hexagon (target/hexagon/imported) arch import - instruction semantics Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 19/34] Hexagon (target/hexagon/imported) arch import - instruction encoding Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 20/34] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 21/34] Hexagon (target/hexagon) generator phase 2 - generate header files Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 22/34] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 23/34] Hexagon (target/hexagon) generater phase 4 - " Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 24/34] Hexagon (target/hexagon) opcode data structures Taylor Simpson
2020-08-26 15:25 ` Richard Henderson
2020-08-26 23:52 ` Taylor Simpson
2020-08-27 4:05 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 25/34] Hexagon (target/hexagon) macros to interface with the generator Taylor Simpson
2020-08-29 0:49 ` Richard Henderson
2020-08-30 20:30 ` Taylor Simpson
2020-08-30 20:59 ` Richard Henderson
2020-08-30 21:20 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 26/34] Hexagon (target/hexagon) macros referenced in instruction semantics Taylor Simpson
2020-08-29 1:16 ` Richard Henderson
2020-08-30 20:23 ` Taylor Simpson
2020-08-30 21:06 ` Richard Henderson
2020-10-08 15:00 ` Taylor Simpson
2020-10-08 17:30 ` Richard Henderson
2020-10-08 18:51 ` Taylor Simpson
2020-10-08 20:02 ` Richard Henderson
2020-10-08 20:54 ` Taylor Simpson
2020-10-09 12:59 ` Richard Henderson
2020-10-09 16:02 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 27/34] Hexagon (target/hexagon) instruction classes Taylor Simpson
2020-08-29 1:37 ` Richard Henderson
2020-08-30 20:04 ` Taylor Simpson
2020-08-30 20:43 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 28/34] Hexagon (target/hexagon) TCG generation helpers Taylor Simpson
2020-08-29 1:48 ` Richard Henderson
2020-08-30 19:53 ` Taylor Simpson
2020-08-30 20:52 ` Richard Henderson
2020-08-30 21:38 ` Taylor Simpson
2020-08-18 15:50 ` [RFC PATCH v3 29/34] Hexagon (target/hexagon) TCG generation Taylor Simpson
2020-08-29 1:58 ` Richard Henderson
2020-08-30 19:49 ` Taylor Simpson
2020-08-18 15:50 ` Taylor Simpson [this message]
2020-08-29 2:02 ` [RFC PATCH v3 30/34] Hexagon (target/hexagon) TCG for instructions with multiple definitions Richard Henderson
2020-08-30 19:48 ` Taylor Simpson
2020-08-30 21:13 ` Richard Henderson
2020-08-30 21:30 ` Taylor Simpson
2020-08-30 23:26 ` Richard Henderson
2020-08-31 17:08 ` Taylor Simpson
2020-08-31 17:29 ` Richard Henderson
2020-08-31 18:14 ` Taylor Simpson
2020-08-31 19:20 ` Richard Henderson
2020-08-31 23:10 ` Taylor Simpson
2020-09-01 2:40 ` Richard Henderson
2020-09-01 4:17 ` Taylor Simpson
2020-09-24 2:56 ` Taylor Simpson
2020-09-24 15:03 ` Richard Henderson
2020-09-24 17:18 ` Taylor Simpson
2020-09-24 19:04 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 31/34] Hexagon (target/hexagon) translation Taylor Simpson
2020-08-29 2:49 ` Richard Henderson
2020-08-30 19:37 ` Taylor Simpson
2020-08-30 23:08 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 32/34] Hexagon (linux-user/hexagon) Linux user emulation Taylor Simpson
2020-08-29 2:59 ` Richard Henderson
2020-08-18 15:50 ` [RFC PATCH v3 33/34] Hexagon (tests/tcg/hexagon) TCG tests Taylor Simpson
2020-08-29 3:05 ` Richard Henderson
2020-09-01 9:57 ` Alessandro Di Federico
2020-08-18 15:50 ` [RFC PATCH v3 34/34] Hexagon build infrastructure Taylor Simpson
2020-08-29 3:19 ` Richard Henderson
2020-09-24 2:35 ` Taylor Simpson
2020-09-25 16:59 ` Philippe Mathieu-Daudé
2020-08-18 16:32 ` [RFC PATCH v3 00/34] Hexagon patch series no-reply
2020-08-29 3:27 ` Richard Henderson
2020-08-30 20:47 ` Taylor Simpson
2020-08-30 23:33 ` Richard Henderson
2020-08-31 17:57 ` Taylor Simpson
2020-08-31 20:43 ` Richard Henderson
2020-08-31 23:48 ` Taylor Simpson
2020-09-07 9:49 ` Rob Landley
2020-09-15 0:41 ` [EXT] " Brian Cain
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