From: Bin Meng <bmeng.cn@gmail.com>
To: "Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
Alistair Francis <alistair@alistair23.me>,
Jason Wang <jasowang@redhat.com>,
Bin Meng <bin.meng@windriver.com>,
qemu-arm@nongnu.org,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Subject: [PATCH v2 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property
Date: Sat, 29 Aug 2020 23:17:35 +0800 [thread overview]
Message-ID: <1598714261-8320-12-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
At present the PHY address of the PHY connected to GEM is hard-coded
to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for
all boards. Add a new 'phy-addr' property so that board can specify
the PHY address for each GEM instance.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
Changes in v2:
- change "phy-addr" default value to BOARD_PHY_ADDRESS
include/hw/net/cadence_gem.h | 2 ++
hw/net/cadence_gem.c | 5 +++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h
index 54e646f..01c6189 100644
--- a/include/hw/net/cadence_gem.h
+++ b/include/hw/net/cadence_gem.h
@@ -73,6 +73,8 @@ typedef struct CadenceGEMState {
/* Mask of register bits which are write 1 to clear */
uint32_t regs_w1c[CADENCE_GEM_MAXREG];
+ /* PHY address */
+ uint8_t phy_addr;
/* PHY registers backing store */
uint16_t phy_regs[32];
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index a93b5c0..d80096b 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
uint32_t phy_addr, reg_num;
phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+ if (phy_addr == s->phy_addr || phy_addr == 0) {
reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
retval &= 0xFFFF0000;
retval |= gem_phy_read(s, reg_num);
@@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val,
uint32_t phy_addr, reg_num;
phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
- if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
+ if (phy_addr == s->phy_addr || phy_addr == 0) {
reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
gem_phy_write(s, reg_num, val);
}
@@ -1682,6 +1682,7 @@ static Property gem_properties[] = {
DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
GEM_MODID_VALUE),
+ DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADDRESS),
DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
num_priority_queues, 1),
DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
--
2.7.4
next prev parent reply other threads:[~2020-08-29 15:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-29 15:17 [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-08-29 15:17 ` [PATCH v2 01/16] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-08-29 15:17 ` [PATCH v2 02/16] hw/riscv: hart: " Bin Meng
2020-08-29 15:17 ` [PATCH v2 03/16] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-08-29 15:17 ` [PATCH v2 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-08-29 15:17 ` [PATCH v2 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-08-29 15:17 ` [PATCH v2 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-08-29 15:17 ` [PATCH v2 07/16] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-08-29 15:17 ` [PATCH v2 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-08-29 15:17 ` [PATCH v2 09/16] hw/dma: Add SiFive platform DMA controller emulation Bin Meng
2020-08-29 15:17 ` [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-08-29 15:17 ` Bin Meng [this message]
2020-08-29 15:17 ` [PATCH v2 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Bin Meng
2020-08-29 15:17 ` [PATCH v2 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-08-29 15:17 ` [PATCH v2 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-08-29 15:17 ` [PATCH v2 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-08-29 15:17 ` [PATCH v2 16/16] hw/riscv: sifive_u: Connect a DMA controller Bin Meng
2020-08-30 12:56 ` [PATCH v2 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Leif Lindholm
2020-08-30 22:15 ` Bin Meng
2020-08-30 23:35 ` Leif Lindholm
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