From: Bin Meng <bmeng.cn@gmail.com>
To: "Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: [PATCH v3 16/16] hw/riscv: sifive_u: Connect a DMA controller
Date: Tue, 1 Sep 2020 09:39:11 +0800 [thread overview]
Message-ID: <1598924352-89526-17-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1598924352-89526-1-git-send-email-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
SiFive FU540 SoC integrates a platform DMA controller with 4 DMA
channels. This connects the exsiting SiFive PDMA model to the SoC,
and adds its device tree data as well.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
(no changes since v1)
include/hw/riscv/sifive_u.h | 11 +++++++++++
hw/riscv/sifive_u.c | 30 ++++++++++++++++++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 42 insertions(+)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index d3c0c00..793000a 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -19,6 +19,7 @@
#ifndef HW_SIFIVE_U_H
#define HW_SIFIVE_U_H
+#include "hw/dma/sifive_pdma.h"
#include "hw/net/cadence_gem.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_cpu.h"
@@ -43,6 +44,7 @@ typedef struct SiFiveUSoCState {
SiFiveUPRCIState prci;
SIFIVEGPIOState gpio;
SiFiveUOTPState otp;
+ SiFivePDMAState dma;
CadenceGEMState gem;
uint32_t serial;
@@ -72,6 +74,7 @@ enum {
SIFIVE_U_MROM,
SIFIVE_U_CLINT,
SIFIVE_U_L2CC,
+ SIFIVE_U_PDMA,
SIFIVE_U_L2LIM,
SIFIVE_U_PLIC,
SIFIVE_U_PRCI,
@@ -108,6 +111,14 @@ enum {
SIFIVE_U_GPIO_IRQ13 = 20,
SIFIVE_U_GPIO_IRQ14 = 21,
SIFIVE_U_GPIO_IRQ15 = 22,
+ SIFIVE_U_PDMA_IRQ0 = 23,
+ SIFIVE_U_PDMA_IRQ1 = 24,
+ SIFIVE_U_PDMA_IRQ2 = 25,
+ SIFIVE_U_PDMA_IRQ3 = 26,
+ SIFIVE_U_PDMA_IRQ4 = 27,
+ SIFIVE_U_PDMA_IRQ5 = 28,
+ SIFIVE_U_PDMA_IRQ6 = 29,
+ SIFIVE_U_PDMA_IRQ7 = 30,
SIFIVE_U_GEM_IRQ = 0x35
};
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2bc3992..7997537 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -14,6 +14,7 @@
* 4) GPIO (General Purpose Input/Output Controller)
* 5) OTP (One-Time Programmable) memory with stored serial number
* 6) GEM (Gigabit Ethernet Controller) and management block
+ * 7) DMA (Direct Memory Access Controller)
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -73,6 +74,7 @@ static const struct MemmapEntry {
[SIFIVE_U_MROM] = { 0x1000, 0xf000 },
[SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
[SIFIVE_U_L2CC] = { 0x2010000, 0x1000 },
+ [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 },
[SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
[SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
[SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
@@ -303,6 +305,22 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart");
g_free(nodename);
+ nodename = g_strdup_printf("/soc/dma@%lx",
+ (long)memmap[SIFIVE_U_PDMA].base);
+ qemu_fdt_add_subnode(fdt, nodename);
+ qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1);
+ qemu_fdt_setprop_cells(fdt, nodename, "interrupts",
+ SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2,
+ SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5,
+ SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7);
+ qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "reg",
+ 0x0, memmap[SIFIVE_U_PDMA].base,
+ 0x0, memmap[SIFIVE_U_PDMA].size);
+ qemu_fdt_setprop_string(fdt, nodename, "compatible",
+ "sifive,fu540-c000-pdma");
+ g_free(nodename);
+
nodename = g_strdup_printf("/soc/cache-controller@%lx",
(long)memmap[SIFIVE_U_L2CC].base);
qemu_fdt_add_subnode(fdt, nodename);
@@ -627,6 +645,7 @@ static void sifive_u_soc_instance_init(Object *obj)
object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM);
object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO);
+ object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA);
}
static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
@@ -730,6 +749,17 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_U_GPIO_IRQ0 + i));
}
+ /* PDMA */
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base);
+
+ /* Connect PDMA interrupts to the PLIC */
+ for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+ qdev_get_gpio_in(DEVICE(s->plic),
+ SIFIVE_U_PDMA_IRQ0 + i));
+ }
+
qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
return;
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 9032cb0..e53ab1e 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -22,6 +22,7 @@ config SIFIVE_U
select CADENCE
select HART
select SIFIVE
+ select SIFIVE_PDMA
select UNIMP
config SPIKE
--
2.7.4
next prev parent reply other threads:[~2020-09-01 1:47 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 1:38 [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-09-01 1:38 ` [PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-09-01 9:36 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 02/16] hw/riscv: hart: " Bin Meng
2020-09-01 9:37 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 03/16] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-09-01 9:37 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-09-01 1:39 ` [PATCH v3 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-09-04 17:47 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-09-01 1:39 ` [PATCH v3 07/16] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-09-04 19:30 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-09-01 9:42 ` Philippe Mathieu-Daudé
2020-09-01 10:27 ` Bin Meng
2020-09-01 17:56 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 09/16] hw/dma: Add SiFive platform DMA controller emulation Bin Meng
2020-09-04 20:25 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-09-04 19:33 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-09-01 9:43 ` Philippe Mathieu-Daudé
2020-09-02 10:45 ` Edgar E. Iglesias
2020-09-04 19:34 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Bin Meng
2020-09-01 9:45 ` Philippe Mathieu-Daudé
2020-09-02 0:16 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-09-01 9:46 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-09-01 9:47 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-09-01 9:49 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` Bin Meng [this message]
2020-09-04 19:36 ` [PATCH v3 16/16] hw/riscv: sifive_u: Connect a DMA controller Alistair Francis
2020-09-04 20:29 ` [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Alistair Francis
2020-09-06 1:08 ` Leif Lindholm
2020-09-07 10:24 ` Bin Meng
2020-09-07 17:27 ` Leif Lindholm
2020-09-08 1:15 ` Bin Meng
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