From: Bin Meng <bmeng.cn@gmail.com>
To: "Alistair Francis" <Alistair.Francis@wdc.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Bin Meng <bin.meng@windriver.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Subject: [PATCH v3 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs
Date: Tue, 1 Sep 2020 09:39:01 +0800 [thread overview]
Message-ID: <1598924352-89526-7-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1598924352-89526-1-git-send-email-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board
wires 4 of them out. Let's connect all 5 MMUARTs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++
hw/riscv/microchip_pfsoc.c | 30 ++++++++++++++++++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 51 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h
index 1953ef1..a5efa1d 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -22,6 +22,8 @@
#ifndef HW_MICROCHIP_PFSOC_H
#define HW_MICROCHIP_PFSOC_H
+#include "hw/char/mchp_pfsoc_mmuart.h"
+
typedef struct MicrochipPFSoCState {
/*< private >*/
DeviceState parent_obj;
@@ -32,6 +34,11 @@ typedef struct MicrochipPFSoCState {
RISCVHartArrayState e_cpus;
RISCVHartArrayState u_cpus;
DeviceState *plic;
+ MchpPfSoCMMUartState *serial0;
+ MchpPfSoCMMUartState *serial1;
+ MchpPfSoCMMUartState *serial2;
+ MchpPfSoCMMUartState *serial3;
+ MchpPfSoCMMUartState *serial4;
} MicrochipPFSoCState;
#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc"
@@ -64,14 +71,27 @@ enum {
MICROCHIP_PFSOC_L2CC,
MICROCHIP_PFSOC_L2LIM,
MICROCHIP_PFSOC_PLIC,
+ MICROCHIP_PFSOC_MMUART0,
MICROCHIP_PFSOC_SYSREG,
MICROCHIP_PFSOC_MPUCFG,
+ MICROCHIP_PFSOC_MMUART1,
+ MICROCHIP_PFSOC_MMUART2,
+ MICROCHIP_PFSOC_MMUART3,
+ MICROCHIP_PFSOC_MMUART4,
MICROCHIP_PFSOC_ENVM_CFG,
MICROCHIP_PFSOC_ENVM_DATA,
MICROCHIP_PFSOC_IOSCB_CFG,
MICROCHIP_PFSOC_DRAM,
};
+enum {
+ MICROCHIP_PFSOC_MMUART0_IRQ = 90,
+ MICROCHIP_PFSOC_MMUART1_IRQ = 91,
+ MICROCHIP_PFSOC_MMUART2_IRQ = 92,
+ MICROCHIP_PFSOC_MMUART3_IRQ = 93,
+ MICROCHIP_PFSOC_MMUART4_IRQ = 94,
+};
+
#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1
#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index d946b2a..cee959a 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -11,6 +11,7 @@
* 0) CLINT (Core Level Interruptor)
* 1) PLIC (Platform Level Interrupt Controller)
* 2) eNVM (Embedded Non-Volatile Memory)
+ * 3) MMUARTs (Multi-Mode UART)
*
* This board currently generates devicetree dynamically that indicates at least
* two harts and up to five harts.
@@ -38,6 +39,7 @@
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/sysbus.h"
+#include "chardev/char.h"
#include "hw/cpu/cluster.h"
#include "target/riscv/cpu.h"
#include "hw/misc/unimp.h"
@@ -46,6 +48,7 @@
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/microchip_pfsoc.h"
+#include "sysemu/sysemu.h"
/*
* The BIOS image used by this machine is called Hart Software Services (HSS).
@@ -69,8 +72,13 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
[MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
[MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
+ [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
[MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
[MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
+ [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
+ [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
+ [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
+ [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
[MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
[MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 },
@@ -215,6 +223,28 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
memmap[MICROCHIP_PFSOC_MPUCFG].base,
memmap[MICROCHIP_PFSOC_MPUCFG].size);
+ /* MMUARTs */
+ s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART0].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
+ serial_hd(0));
+ s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART1].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
+ serial_hd(1));
+ s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART2].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
+ serial_hd(2));
+ s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART3].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
+ serial_hd(3));
+ s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
+ memmap[MICROCHIP_PFSOC_MMUART4].base,
+ qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
+ serial_hd(4));
+
/* eNVM */
memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 3292fae..ceb7c16 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -54,3 +54,4 @@ config MICROCHIP_PFSOC
select HART
select SIFIVE
select UNIMP
+ select MCHP_PFSOC_MMUART
--
2.7.4
next prev parent reply other threads:[~2020-09-01 1:46 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-01 1:38 [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-09-01 1:38 ` [PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-09-01 9:36 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 02/16] hw/riscv: hart: " Bin Meng
2020-09-01 9:37 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 03/16] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-09-01 9:37 ` Philippe Mathieu-Daudé
2020-09-01 1:38 ` [PATCH v3 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-09-01 1:39 ` [PATCH v3 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-09-04 17:47 ` Alistair Francis
2020-09-01 1:39 ` Bin Meng [this message]
2020-09-01 1:39 ` [PATCH v3 07/16] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-09-04 19:30 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-09-01 9:42 ` Philippe Mathieu-Daudé
2020-09-01 10:27 ` Bin Meng
2020-09-01 17:56 ` Philippe Mathieu-Daudé
2020-09-04 19:08 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 09/16] hw/dma: Add SiFive platform DMA controller emulation Bin Meng
2020-09-04 20:25 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-09-04 19:33 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-09-01 9:43 ` Philippe Mathieu-Daudé
2020-09-02 10:45 ` Edgar E. Iglesias
2020-09-04 19:34 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Bin Meng
2020-09-01 9:45 ` Philippe Mathieu-Daudé
2020-09-02 0:16 ` Alistair Francis
2020-09-01 1:39 ` [PATCH v3 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-09-01 9:46 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-09-01 9:47 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-09-01 9:49 ` Philippe Mathieu-Daudé
2020-09-01 1:39 ` [PATCH v3 16/16] hw/riscv: sifive_u: Connect a DMA controller Bin Meng
2020-09-04 19:36 ` Alistair Francis
2020-09-04 20:29 ` [PATCH v3 00/16] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Alistair Francis
2020-09-06 1:08 ` Leif Lindholm
2020-09-07 10:24 ` Bin Meng
2020-09-07 17:27 ` Leif Lindholm
2020-09-08 1:15 ` Bin Meng
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