From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com
Subject: Re: [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions
Date: Wed, 11 Aug 2021 07:56:32 -1000 [thread overview]
Message-ID: <15f69497-3baf-abf1-ba9e-91ac1e883d63@linaro.org> (raw)
In-Reply-To: <538f3928-f681-cb9e-7850-48469ea4ccd5@c-sky.com>
On 8/11/21 4:57 AM, LIU Zhiwei wrote:
> I still don't know why the value written sign-extended. If that's the the rule of final
> specification, I will try to obey it although our Linux will not depend on the high part.
The text that I'm looking at is
https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf
3.1.6.2 Base ISA Control in mstatus Register
In the fifth paragraph, the requirement for sign-extension is detailed.
r~
next prev parent reply other threads:[~2021-08-11 17:57 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-05 2:52 [RFC PATCH 00/13] Support UXL field in mstatus LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 01/13] target/riscv: Add UXL to tb flags LIU Zhiwei
2021-08-05 6:00 ` Alistair Francis
2021-08-05 19:01 ` Richard Henderson
2021-08-06 2:49 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 02/13] target/riscv: Support UXL32 for branch instructions LIU Zhiwei
2021-08-05 19:06 ` Richard Henderson
2021-08-09 1:45 ` LIU Zhiwei
2021-08-09 19:34 ` Richard Henderson
2021-08-11 14:57 ` LIU Zhiwei
2021-08-11 17:56 ` Richard Henderson [this message]
2021-08-11 22:40 ` LIU Zhiwei
2021-08-12 4:42 ` Richard Henderson
2021-08-12 5:03 ` LIU Zhiwei
2021-08-12 6:12 ` Richard Henderson
2021-08-12 7:20 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 03/13] target/riscv: Support UXL32 on 64-bit cpu for load/store LIU Zhiwei
2021-08-05 19:08 ` Richard Henderson
2021-08-09 1:50 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 04/13] target/riscv: Support UXL32 for slit/sltiu LIU Zhiwei
2021-08-05 19:09 ` Richard Henderson
2021-08-09 7:28 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 05/13] target/riscv: Support UXL32 for shift instruction LIU Zhiwei
2021-08-05 22:17 ` Richard Henderson
2021-08-09 7:51 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 06/13] target/riscv: Fix div instructions LIU Zhiwei
2021-08-05 22:18 ` Richard Henderson
2021-08-09 7:53 ` LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 07/13] target/riscv: Support UXL32 for RVM LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 08/13] target/riscv: Support UXL32 for vector instructions LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 09/13] target/riscv: Support UXL32 for atomic instructions LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 10/13] target/riscv: Support UXL32 for float instructions LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 11/13] target/riscv: Fix srow LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 12/13] target/riscv: Support UXL32 for RVB LIU Zhiwei
2021-08-05 2:53 ` [RFC PATCH 13/13] target/riscv: Changing the width of U-mode CSR LIU Zhiwei
2021-08-05 6:01 ` [RFC PATCH 00/13] Support UXL field in mstatus Alistair Francis
2021-08-05 7:14 ` LIU Zhiwei
2021-08-05 7:20 ` Bin Meng
2021-08-05 8:10 ` LIU Zhiwei
2021-08-06 10:05 ` Alistair Francis
2021-08-09 1:25 ` LIU Zhiwei
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