From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org,
laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com
Subject: [PATCH v6 14/35] Hexagon (target/hexagon) instruction printing
Date: Thu, 7 Jan 2021 22:28:45 -0600 [thread overview]
Message-ID: <1610080146-14968-15-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1610080146-14968-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/printinsn.h | 28 ++++++++
target/hexagon/printinsn.c | 158 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 186 insertions(+)
create mode 100644 target/hexagon/printinsn.h
create mode 100644 target/hexagon/printinsn.c
diff --git a/target/hexagon/printinsn.h b/target/hexagon/printinsn.h
new file mode 100644
index 0000000..0e629b2
--- /dev/null
+++ b/target/hexagon/printinsn.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_PRINTINSN_H
+#define HEXAGON_PRINTINSN_H
+
+#include "qemu/osdep.h"
+#include "insn.h"
+
+extern void snprint_a_pkt_disas(char *buf, int n, Packet *pkt, uint32_t *words,
+ target_ulong pc);
+extern void snprint_a_pkt_debug(char *buf, int n, Packet *pkt);
+
+#endif
diff --git a/target/hexagon/printinsn.c b/target/hexagon/printinsn.c
new file mode 100644
index 0000000..8315d56
--- /dev/null
+++ b/target/hexagon/printinsn.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "opcodes.h"
+#include "printinsn.h"
+#include "insn.h"
+#include "reg_fields.h"
+#include "internal.h"
+
+static const char *sreg2str(unsigned int reg)
+{
+ if (reg < TOTAL_PER_THREAD_REGS) {
+ return hexagon_regnames[reg];
+ } else {
+ return "???";
+ }
+}
+
+static const char *creg2str(unsigned int reg)
+{
+ return sreg2str(reg + HEX_REG_SA0);
+}
+
+static void snprintinsn(char *buf, int n, Insn * insn)
+{
+ switch (insn->opcode) {
+#define DEF_VECX_PRINTINFO(TAG, FMT, ...) DEF_PRINTINFO(TAG, FMT, __VA_ARGS__)
+#define DEF_PRINTINFO(TAG, FMT, ...) \
+ case TAG: \
+ snprintf(buf, n, FMT, __VA_ARGS__);\
+ break;
+#include "printinsn_generated.h"
+#undef DEF_VECX_PRINTINFO
+#undef DEF_PRINTINFO
+ }
+}
+
+void snprint_a_pkt_disas(char *buf, int n, Packet *pkt, uint32_t *words,
+ target_ulong pc)
+{
+ char tmpbuf[128];
+ buf[0] = '\0';
+ bool has_endloop0 = false;
+ bool has_endloop1 = false;
+ bool has_endloop01 = false;
+
+ for (int i = 0; i < pkt->num_insns; i++) {
+ if (pkt->insn[i].part1) {
+ continue;
+ }
+
+ /* We'll print the endloop's at the end of the packet */
+ if (pkt->insn[i].opcode == J2_endloop0) {
+ has_endloop0 = true;
+ continue;
+ }
+ if (pkt->insn[i].opcode == J2_endloop1) {
+ has_endloop1 = true;
+ continue;
+ }
+ if (pkt->insn[i].opcode == J2_endloop01) {
+ has_endloop01 = true;
+ continue;
+ }
+
+ snprintf(tmpbuf, 127, "0x" TARGET_FMT_lx "\t", words[i]);
+ strncat(buf, tmpbuf, n);
+
+ if (i == 0) {
+ strncat(buf, "{", n);
+ }
+
+ snprintinsn(tmpbuf, 127, &(pkt->insn[i]));
+ strncat(buf, "\t", n);
+ strncat(buf, tmpbuf, n);
+
+ if (i < pkt->num_insns - 1) {
+ /*
+ * Subinstructions are two instructions encoded
+ * in the same word. Print them on the same line.
+ */
+ if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN)) {
+ strncat(buf, "; ", n);
+ snprintinsn(tmpbuf, 127, &(pkt->insn[i + 1]));
+ strncat(buf, tmpbuf, n);
+ i++;
+ } else if (pkt->insn[i + 1].opcode != J2_endloop0 &&
+ pkt->insn[i + 1].opcode != J2_endloop1 &&
+ pkt->insn[i + 1].opcode != J2_endloop01) {
+ pc += 4;
+ snprintf(tmpbuf, 127, "\n0x" TARGET_FMT_lx ": ", pc);
+ strncat(buf, tmpbuf, n);
+ }
+ }
+ }
+ strncat(buf, " }", n);
+ if (has_endloop0) {
+ strncat(buf, " :endloop0", n);
+ }
+ if (has_endloop1) {
+ strncat(buf, " :endloop1", n);
+ }
+ if (has_endloop01) {
+ strncat(buf, " :endloop01", n);
+ }
+ strncat(buf, "\n", n);
+}
+
+void snprint_a_pkt_debug(char *buf, int n, Packet *pkt)
+{
+ char tmpbuf[128];
+ buf[0] = '\0';
+ int slot, opcode;
+
+ if (pkt->num_insns > 1) {
+ strncat(buf, "\n{\n", n);
+ }
+
+ for (int i = 0; i < pkt->num_insns; i++) {
+ if (pkt->insn[i].part1) {
+ continue;
+ }
+ snprintinsn(tmpbuf, 127, &(pkt->insn[i]));
+ strncat(buf, "\t", n);
+ strncat(buf, tmpbuf, n);
+
+ if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN)) {
+ strncat(buf, " //subinsn", n);
+ }
+ if (pkt->insn[i].extension_valid) {
+ strncat(buf, " //constant extended", n);
+ }
+ slot = pkt->insn[i].slot;
+ opcode = pkt->insn[i].opcode;
+ snprintf(tmpbuf, 127, " //slot=%d:tag=%s", slot, opcode_names[opcode]);
+ strncat(buf, tmpbuf, n);
+
+ strncat(buf, "\n", n);
+ }
+ if (pkt->num_insns > 1) {
+ strncat(buf, "}\n", n);
+ }
+}
--
2.7.4
next prev parent reply other threads:[~2021-01-08 4:42 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-08 4:28 [PATCH v6 00/35] Hexagon patch series Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 01/35] Hexagon Update MAINTAINERS file Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 02/35] Hexagon (target/hexagon) README Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 03/35] Hexagon (include/elf.h) ELF machine definition Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 04/35] Hexagon (target/hexagon) scalar core definition Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 05/35] Hexagon (disas) disassembler Taylor Simpson
2021-01-09 21:37 ` Philippe Mathieu-Daudé
2021-01-11 21:14 ` Taylor Simpson
2021-01-11 22:20 ` Philippe Mathieu-Daudé
2021-01-12 9:35 ` Daniel P. Berrangé
2021-01-08 4:28 ` [PATCH v6 06/35] Hexagon (target/hexagon) register names Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 07/35] Hexagon (target/hexagon) scalar core helpers Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 08/35] Hexagon (target/hexagon) GDB Stub Taylor Simpson
2021-01-09 21:44 ` Philippe Mathieu-Daudé
2021-01-08 4:28 ` [PATCH v6 09/35] Hexagon (target/hexagon) architecture types Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 10/35] Hexagon (target/hexagon) instruction and packet types Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 11/35] Hexagon (target/hexagon) register fields Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 12/35] Hexagon (target/hexagon) instruction attributes Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 13/35] Hexagon (target/hexagon) instruction/packet decode Taylor Simpson
2021-01-08 4:28 ` Taylor Simpson [this message]
2021-01-09 22:41 ` [PATCH v6 14/35] Hexagon (target/hexagon) instruction printing Philippe Mathieu-Daudé
2021-01-08 4:28 ` [PATCH v6 15/35] Hexagon (target/hexagon/arch.[ch]) utility functions Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 16/35] Hexagon (target/hexagon/conv_emu.[ch]) " Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 17/35] Hexagon (target/hexagon/fma_emu.[ch]) " Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 18/35] Hexagon (target/hexagon/imported) arch import Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 19/35] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 20/35] Hexagon (target/hexagon) generator phase 2 - generate header files Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 21/35] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 22/35] Hexagon (target/hexagon) generater phase 4 - " Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 23/35] Hexagon (target/hexagon) opcode data structures Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 24/35] Hexagon (target/hexagon) macros Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 25/35] Hexagon (target/hexagon) instruction classes Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 26/35] Hexagon (target/hexagon) TCG generation Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 27/35] Hexagon (target/hexagon) TCG for instructions with multiple definitions Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 28/35] Hexagon (target/hexagon) TCG for floating point instructions Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 29/35] Hexagon (target/hexagon) translation Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 30/35] Hexagon (linux-user/hexagon) Linux user emulation Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 31/35] Hexagon (tests/tcg/hexagon) TCG tests Taylor Simpson
2021-01-12 12:04 ` Alex Bennée
2021-01-12 17:06 ` Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 32/35] Hexagon build infrastructure Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 33/35] Add Dockerfile for hexagon Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 34/35] Auto-import Docker support files Taylor Simpson
2021-01-12 11:58 ` Alex Bennée
2021-01-12 13:53 ` Alessandro Di Federico via
2021-01-12 18:26 ` Alex Bennée
2021-01-21 12:20 ` ale--- via
2021-01-08 4:29 ` [PATCH v6 35/35] Add newline when generating Dockerfile Taylor Simpson
2021-01-12 11:59 ` Alex Bennée
2021-01-08 5:16 ` [PATCH v6 00/35] Hexagon patch series no-reply
2021-01-12 19:42 ` Alex Bennée
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