From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org,
laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com
Subject: [PATCH v6 28/35] Hexagon (target/hexagon) TCG for floating point instructions
Date: Thu, 7 Jan 2021 22:28:59 -0600 [thread overview]
Message-ID: <1610080146-14968-29-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1610080146-14968-1-git-send-email-tsimpson@quicinc.com>
The imported code uses host floating point. We override them
to use qemu softfloat
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/gen_tcg.h | 121 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 121 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 35568d1..d605b1e 100644
--- a/target/hexagon/gen_tcg.h
+++ b/target/hexagon/gen_tcg.h
@@ -195,4 +195,125 @@
#define fGEN_TCG_S4_stored_locked(SHORTCODE) \
do { SHORTCODE; READ_PREG(PdV, PdN); } while (0)
+/* Floating point */
+#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
+ gen_helper_conv_sf2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
+ gen_helper_conv_df2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
+ gen_helper_conv_uw2sf(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
+ gen_helper_conv_uw2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
+ gen_helper_conv_w2sf(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
+ gen_helper_conv_w2df(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
+ gen_helper_conv_ud2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
+ gen_helper_conv_ud2df(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
+ gen_helper_conv_d2sf(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
+ gen_helper_conv_d2df(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
+ gen_helper_conv_sf2uw(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
+ gen_helper_conv_sf2w(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
+ gen_helper_conv_sf2ud(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
+ gen_helper_conv_sf2d(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
+ gen_helper_conv_df2uw(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
+ gen_helper_conv_df2w(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
+ gen_helper_conv_df2ud(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
+ gen_helper_conv_df2d(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
+ gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
+ gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
+ gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
+ gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV)
+#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
+ gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
+ gen_helper_conv_df2w_chop(RdV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
+ gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
+ gen_helper_conv_df2d_chop(RddV, cpu_env, RssV)
+#define fGEN_TCG_F2_sfadd(SHORTCODE) \
+ gen_helper_sfadd(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfsub(SHORTCODE) \
+ gen_helper_sfsub(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
+ gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
+ gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
+ gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
+ gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfmax(SHORTCODE) \
+ gen_helper_sfmax(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfmin(SHORTCODE) \
+ gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sfclass(SHORTCODE) \
+ do { \
+ TCGv imm = tcg_const_tl(uiV); \
+ gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
+ tcg_temp_free(imm); \
+ } while (0)
+#define fGEN_TCG_F2_sffixupn(SHORTCODE) \
+ gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffixupd(SHORTCODE) \
+ gen_helper_sffixupd(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffixupr(SHORTCODE) \
+ gen_helper_sffixupr(RdV, cpu_env, RsV)
+#define fGEN_TCG_F2_dfadd(SHORTCODE) \
+ gen_helper_dfadd(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfsub(SHORTCODE) \
+ gen_helper_dfsub(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmax(SHORTCODE) \
+ gen_helper_dfmax(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmin(SHORTCODE) \
+ gen_helper_dfmin(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
+ gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
+ gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
+ gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
+ gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfclass(SHORTCODE) \
+ do { \
+ TCGv imm = tcg_const_tl(uiV); \
+ gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
+ tcg_temp_free(imm); \
+ } while (0)
+#define fGEN_TCG_F2_sfmpy(SHORTCODE) \
+ gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
+#define fGEN_TCG_F2_sffma(SHORTCODE) \
+ gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
+ gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV)
+#define fGEN_TCG_F2_sffms(SHORTCODE) \
+ gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
+ gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV)
+#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
+ gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV)
+
+#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
+ gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV)
+#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
+ gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
+
#endif
--
2.7.4
next prev parent reply other threads:[~2021-01-08 5:10 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-08 4:28 [PATCH v6 00/35] Hexagon patch series Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 01/35] Hexagon Update MAINTAINERS file Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 02/35] Hexagon (target/hexagon) README Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 03/35] Hexagon (include/elf.h) ELF machine definition Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 04/35] Hexagon (target/hexagon) scalar core definition Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 05/35] Hexagon (disas) disassembler Taylor Simpson
2021-01-09 21:37 ` Philippe Mathieu-Daudé
2021-01-11 21:14 ` Taylor Simpson
2021-01-11 22:20 ` Philippe Mathieu-Daudé
2021-01-12 9:35 ` Daniel P. Berrangé
2021-01-08 4:28 ` [PATCH v6 06/35] Hexagon (target/hexagon) register names Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 07/35] Hexagon (target/hexagon) scalar core helpers Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 08/35] Hexagon (target/hexagon) GDB Stub Taylor Simpson
2021-01-09 21:44 ` Philippe Mathieu-Daudé
2021-01-08 4:28 ` [PATCH v6 09/35] Hexagon (target/hexagon) architecture types Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 10/35] Hexagon (target/hexagon) instruction and packet types Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 11/35] Hexagon (target/hexagon) register fields Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 12/35] Hexagon (target/hexagon) instruction attributes Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 13/35] Hexagon (target/hexagon) instruction/packet decode Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 14/35] Hexagon (target/hexagon) instruction printing Taylor Simpson
2021-01-09 22:41 ` Philippe Mathieu-Daudé
2021-01-08 4:28 ` [PATCH v6 15/35] Hexagon (target/hexagon/arch.[ch]) utility functions Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 16/35] Hexagon (target/hexagon/conv_emu.[ch]) " Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 17/35] Hexagon (target/hexagon/fma_emu.[ch]) " Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 18/35] Hexagon (target/hexagon/imported) arch import Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 19/35] Hexagon (target/hexagon) generator phase 1 - C preprocessor for semantics Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 20/35] Hexagon (target/hexagon) generator phase 2 - generate header files Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 21/35] Hexagon (target/hexagon) generator phase 3 - C preprocessor for decode tree Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 22/35] Hexagon (target/hexagon) generater phase 4 - " Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 23/35] Hexagon (target/hexagon) opcode data structures Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 24/35] Hexagon (target/hexagon) macros Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 25/35] Hexagon (target/hexagon) instruction classes Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 26/35] Hexagon (target/hexagon) TCG generation Taylor Simpson
2021-01-08 4:28 ` [PATCH v6 27/35] Hexagon (target/hexagon) TCG for instructions with multiple definitions Taylor Simpson
2021-01-08 4:28 ` Taylor Simpson [this message]
2021-01-08 4:29 ` [PATCH v6 29/35] Hexagon (target/hexagon) translation Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 30/35] Hexagon (linux-user/hexagon) Linux user emulation Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 31/35] Hexagon (tests/tcg/hexagon) TCG tests Taylor Simpson
2021-01-12 12:04 ` Alex Bennée
2021-01-12 17:06 ` Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 32/35] Hexagon build infrastructure Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 33/35] Add Dockerfile for hexagon Taylor Simpson
2021-01-08 4:29 ` [PATCH v6 34/35] Auto-import Docker support files Taylor Simpson
2021-01-12 11:58 ` Alex Bennée
2021-01-12 13:53 ` Alessandro Di Federico via
2021-01-12 18:26 ` Alex Bennée
2021-01-21 12:20 ` ale--- via
2021-01-08 4:29 ` [PATCH v6 35/35] Add newline when generating Dockerfile Taylor Simpson
2021-01-12 11:59 ` Alex Bennée
2021-01-08 5:16 ` [PATCH v6 00/35] Hexagon patch series no-reply
2021-01-12 19:42 ` Alex Bennée
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